Commit 268bfa44 by Stan Cox

Use TARGET* macros.

From-SVN: r10742
parent c8c5cb99
...@@ -72,6 +72,12 @@ ...@@ -72,6 +72,12 @@
;; actually generating RTL. The bCOND or sCOND (emitted immediately ;; actually generating RTL. The bCOND or sCOND (emitted immediately
;; after the tstM or cmp) will actually emit the tstM or cmpM. ;; after the tstM or cmp) will actually emit the tstM or cmpM.
;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in rs6000.h.
(define_attr "cpu" "i386,i486,pentium"
(const (symbol_ref "ix86_cpu_attr")))
(define_insn "tstsi_1" (define_insn "tstsi_1"
[(set (cc0) [(set (cc0)
(match_operand:SI 0 "nonimmediate_operand" "rm"))] (match_operand:SI 0 "nonimmediate_operand" "rm"))]
...@@ -742,22 +748,22 @@ ...@@ -742,22 +748,22 @@
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "push_operand" "=<") [(set (match_operand:SI 0 "push_operand" "=<")
(match_operand:SI 1 "general_operand" "g"))] (match_operand:SI 1 "general_operand" "g"))]
"TARGET_386" "TARGET_PUSH_MEMORY"
"push%L0 %1") "push%L0 %1")
;; On a 486, it is faster to move MEM to a REG and then push, rather than ;; If not a 386, it is faster to move MEM to a REG and then push, rather than
;; push MEM directly. ;; push MEM directly.
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "push_operand" "=<") [(set (match_operand:SI 0 "push_operand" "=<")
(match_operand:SI 1 "nonmemory_operand" "ri"))] (match_operand:SI 1 "nonmemory_operand" "ri"))]
"!TARGET_386 && TARGET_MOVE" "!TARGET_PUSH_MEMORY && TARGET_MOVE"
"push%L0 %1") "push%L0 %1")
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "push_operand" "=<") [(set (match_operand:SI 0 "push_operand" "=<")
(match_operand:SI 1 "general_operand" "ri"))] (match_operand:SI 1 "general_operand" "ri"))]
"!TARGET_386 && !TARGET_MOVE" "!TARGET_PUSH_MEMORY && !TARGET_MOVE"
"push%L0 %1") "push%L0 %1")
;; General case of fullword move. ;; General case of fullword move.
...@@ -819,19 +825,19 @@ ...@@ -819,19 +825,19 @@
(define_insn "" (define_insn ""
[(set (match_operand:HI 0 "push_operand" "=<") [(set (match_operand:HI 0 "push_operand" "=<")
(match_operand:HI 1 "general_operand" "g"))] (match_operand:HI 1 "general_operand" "g"))]
"TARGET_386" "TARGET_PUSH_MEMORY"
"push%W0 %1") "push%W0 %1")
(define_insn "" (define_insn ""
[(set (match_operand:HI 0 "push_operand" "=<") [(set (match_operand:HI 0 "push_operand" "=<")
(match_operand:HI 1 "nonmemory_operand" "ri"))] (match_operand:HI 1 "nonmemory_operand" "ri"))]
"!TARGET_386 && TARGET_MOVE" "!TARGET_PUSH_MEMORY && TARGET_MOVE"
"push%W0 %1") "push%W0 %1")
(define_insn "" (define_insn ""
[(set (match_operand:HI 0 "push_operand" "=<") [(set (match_operand:HI 0 "push_operand" "=<")
(match_operand:HI 1 "general_operand" "ri"))] (match_operand:HI 1 "general_operand" "ri"))]
"!TARGET_386 && !TARGET_MOVE" "!TARGET_PUSH_MEMORY && !TARGET_MOVE"
"push%W0 %1") "push%W0 %1")
;; On i486, an incl and movl are both faster than incw and movw. ;; On i486, an incl and movl are both faster than incw and movw.
...@@ -1629,7 +1635,7 @@ ...@@ -1629,7 +1635,7 @@
"" ""
"* "*
{ {
if ((!TARGET_386 || REGNO (operands[0]) == 0) if ((TARGET_ZERO_EXTEND_WITH_AND || REGNO (operands[0]) == 0)
&& REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1]))
{ {
rtx xops[2]; rtx xops[2];
...@@ -1653,7 +1659,7 @@ ...@@ -1653,7 +1659,7 @@
"" ""
"* "*
{ {
if ((!TARGET_386 || REGNO (operands[0]) == 0) if ((TARGET_ZERO_EXTEND_WITH_AND || REGNO (operands[0]) == 0)
&& REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1]))
{ {
rtx xops[2]; rtx xops[2];
...@@ -1677,7 +1683,7 @@ ...@@ -1677,7 +1683,7 @@
"" ""
"* "*
{ {
if ((!TARGET_386 || REGNO (operands[0]) == 0) if ((TARGET_ZERO_EXTEND_WITH_AND || REGNO (operands[0]) == 0)
&& REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1]))
{ {
rtx xops[2]; rtx xops[2];
...@@ -3003,7 +3009,7 @@ ...@@ -3003,7 +3009,7 @@
if (INTVAL (operands[2]) == 0xffff && REG_P (operands[0]) if (INTVAL (operands[2]) == 0xffff && REG_P (operands[0])
&& (! REG_P (operands[1]) && (! REG_P (operands[1])
|| REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0) || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0)
&& (TARGET_386 || ! rtx_equal_p (operands[0], operands[1]))) && (!TARGET_ZERO_EXTEND_WITH_AND || ! rtx_equal_p (operands[0], operands[1])))
{ {
/* ??? tege: Should forget CC_STATUS only if we clobber a /* ??? tege: Should forget CC_STATUS only if we clobber a
remembered operand. Fix that later. */ remembered operand. Fix that later. */
...@@ -3019,7 +3025,7 @@ ...@@ -3019,7 +3025,7 @@
&& !(REG_P (operands[1]) && NON_QI_REG_P (operands[1])) && !(REG_P (operands[1]) && NON_QI_REG_P (operands[1]))
&& (! REG_P (operands[1]) && (! REG_P (operands[1])
|| REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0) || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0)
&& (TARGET_386 || ! rtx_equal_p (operands[0], operands[1]))) && (!TARGET_ZERO_EXTEND_WITH_AND || ! rtx_equal_p (operands[0], operands[1])))
{ {
/* ??? tege: Should forget CC_STATUS only if we clobber a /* ??? tege: Should forget CC_STATUS only if we clobber a
remembered operand. Fix that later. */ remembered operand. Fix that later. */
...@@ -3676,7 +3682,7 @@ ...@@ -3676,7 +3682,7 @@
{ {
if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1])) if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1]))
{ {
if (!TARGET_386 && INTVAL (operands[2]) == 1) if (TARGET_DOUBLE_WITH_ADD && INTVAL (operands[2]) == 1)
{ {
output_asm_insn (AS2 (mov%L0,%1,%0), operands); output_asm_insn (AS2 (mov%L0,%1,%0), operands);
return AS2 (add%L0,%1,%0); return AS2 (add%L0,%1,%0);
...@@ -4177,7 +4183,7 @@ ...@@ -4177,7 +4183,7 @@
(const_int 1) (const_int 1)
(match_operand:SI 2 "general_operand" "r")) (match_operand:SI 2 "general_operand" "r"))
(match_operand:SI 3 "const_int_operand" "n"))] (match_operand:SI 3 "const_int_operand" "n"))]
"TARGET_386 && GET_CODE (operands[2]) != CONST_INT" "TARGET_BIT_TEST && GET_CODE (operands[2]) != CONST_INT"
"* "*
{ {
CC_STATUS_INIT; CC_STATUS_INIT;
...@@ -4195,7 +4201,7 @@ ...@@ -4195,7 +4201,7 @@
(xor:SI (ashift:SI (const_int 1) (xor:SI (ashift:SI (const_int 1)
(match_operand:SI 1 "general_operand" "r")) (match_operand:SI 1 "general_operand" "r"))
(match_operand:SI 2 "general_operand" "0")))] (match_operand:SI 2 "general_operand" "0")))]
"TARGET_386 && GET_CODE (operands[1]) != CONST_INT" "TARGET_BIT_TEST && GET_CODE (operands[1]) != CONST_INT"
"* "*
{ {
CC_STATUS_INIT; CC_STATUS_INIT;
...@@ -4208,7 +4214,7 @@ ...@@ -4208,7 +4214,7 @@
(xor:SI (match_operand:SI 1 "general_operand" "0") (xor:SI (match_operand:SI 1 "general_operand" "0")
(ashift:SI (const_int 1) (ashift:SI (const_int 1)
(match_operand:SI 2 "general_operand" "r"))))] (match_operand:SI 2 "general_operand" "r"))))]
"TARGET_386 && GET_CODE (operands[2]) != CONST_INT" "TARGET_BIT_TEST && GET_CODE (operands[2]) != CONST_INT"
"* "*
{ {
CC_STATUS_INIT; CC_STATUS_INIT;
......
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