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Commit 2644d4d9 by Jiong Wang Committed by Jiong Wang
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[AArch64, 2/6] Reimplement vector fixed-point intrinsics 

	* config/aarch64/aarch64-builtins.def (scvtf): Register vector modes.
	(ucvtf): Likewise.
	(fcvtzs): Likewise.
	(fcvtzu): Likewise.
	* config/aarch64/aarch64-simd.md
	(<FCVT_F2FIXED:fcvt_fixed_insn><VDQF:mode>3): New.
	(<FCVT_FIXED2F:fcvt_fixed_insn><VDQ_SDI:mode>3): Likewise.
	* config/aarch64/arm_neon.h (vcvt_n_f32_s32): Remove inline assembly.
	Use builtin.
	(vcvt_n_f32_u32): Likewise.
	(vcvt_n_s32_f32): Likewise.
	(vcvt_n_u32_f32): Likewise.
	(vcvtq_n_f32_s32): Likewise.
	(vcvtq_n_f32_u32): Likewise.
	(vcvtq_n_f64_s64): Likewise.
	(vcvtq_n_f64_u64): Likewise.
	(vcvtq_n_s32_f32): Likewise.
	(vcvtq_n_s64_f64): Likewise.
	(vcvtq_n_u32_f32): Likewise.
	(vcvtq_n_u64_f64): Likewise.
	* config/aarch64/iterators.md (VDQ_SDI): New mode iterator.
	(VSDQ_SDI): Likewise.
	(fcvt_target): Support V4DI, V4SI and V2SI.
	(FCVT_TARGET): Likewise.

From-SVN: r237201
parent 3f598afe
Showing with 91 additions and 34 deletions
gcc/ChangeLog
2016-06-08 Jiong Wang <jiong.wang@arm.com> 2016-06-08 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64-builtins.c (TYPES_BINOP_USS): New * config/aarch64/aarch64-builtins.def (scvtf): Register vector modes.
(TYPES_BINOP_SUS): Likewise. (ucvtf): Likewise.
(aarch64_simd_builtin_data): Update include file name. (fcvtzs): Likewise.
(aarch64_builtins): Likewise. (fcvtzu): Likewise.
* config/aarch64/aarch64-simd-builtins.def (scvtf): New entries * config/aarch64/aarch64-simd.md
for conversion between scalar float-point and fixed-point. (<FCVT_F2FIXED:fcvt_fixed_insn><VDQF:mode>3): New.
(ucvtf): Likewise. (<FCVT_FIXED2F:fcvt_fixed_insn><VDQ_SDI:mode>3): Likewise.
(fcvtzs): Likewise. * config/aarch64/arm_neon.h (vcvt_n_f32_s32): Remove inline assembly.
(fcvtzu): Likewise. Use builtin.
* config/aarch64/aarch64.md (vcvt_n_f32_u32): Likewise.
(<FCVT_F2FIXED:fcvt_fixed_insn><GPF:mode>3: New (vcvt_n_s32_f32): Likewise.
pattern for conversion between scalar float to fixed-pointer. (vcvt_n_u32_f32): Likewise.
(<FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>: Likewise. (vcvtq_n_f32_s32): Likewise.
(UNSPEC_FCVTZS): New UNSPEC enumeration. (vcvtq_n_f32_u32): Likewise.
(UNSPEC_FCVTZU): Likewise. (vcvtq_n_f64_s64): Likewise.
(UNSPEC_SCVTF): Likewise. (vcvtq_n_f64_u64): Likewise.
(UNSPEC_UCVTF): Likewise. (vcvtq_n_s32_f32): Likewise.
* config/aarch64/arm_neon.h (vcvtd_n_f64_s64): Remove inline assembly. (vcvtq_n_s64_f64): Likewise.
(vcvtq_n_u32_f32): Likewise.
(vcvtq_n_u64_f64): Likewise.
* config/aarch64/iterators.md (VDQ_SDI): New mode iterator.
(VSDQ_SDI): Likewise.
(fcvt_target): Support V4DI, V4SI and V2SI.
(FCVT_TARGET): Likewise.
2016-06-08 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64-builtins.c (TYPES_BINOP_USS): New
(TYPES_BINOP_SUS): Likewise.
(aarch64_simd_builtin_data): Update include file name.
(aarch64_builtins): Likewise.
* config/aarch64/aarch64-simd-builtins.def (scvtf): New entries
for conversion between scalar float-point and fixed-point.
(ucvtf): Likewise.
(fcvtzs): Likewise.
(fcvtzu): Likewise.
* config/aarch64/aarch64.md
(<FCVT_F2FIXED:fcvt_fixed_insn><GPF:mode>3: New
pattern for conversion between scalar float to fixed-pointer.
(<FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>: Likewise.
(UNSPEC_FCVTZS): New UNSPEC enumeration.
(UNSPEC_FCVTZU): Likewise.
(UNSPEC_SCVTF): Likewise.
(UNSPEC_UCVTF): Likewise.
* config/aarch64/arm_neon.h (vcvtd_n_f64_s64): Remove inline assembly.
Use builtin. Use builtin.
(vcvtd_n_f64_u64): Likewise. (vcvtd_n_f64_u64): Likewise.
(vcvtd_n_s64_f64): Likewise. (vcvtd_n_s64_f64): Likewise.
(vcvtd_n_u64_f64): Likewise. (vcvtd_n_u64_f64): Likewise.
(vcvtd_n_f32_s32): Likewise. (vcvtd_n_f32_s32): Likewise.
(vcvts_n_f32_u32): Likewise. (vcvts_n_f32_u32): Likewise.
(vcvtd_n_s32_f32): Likewise. (vcvtd_n_s32_f32): Likewise.
(vcvts_n_u32_f32): Likewise. (vcvts_n_u32_f32): Likewise.
* config/aarch64/iterators.md (fcvt_target): Support integer to float * config/aarch64/iterators.md (fcvt_target): Support integer to float
mapping. mapping.
(FCVT_TARGET): Likewise. (FCVT_TARGET): Likewise.
(FCVT_FIXED2F): New iterator. (FCVT_FIXED2F): New iterator.
(FCVT_F2FIXED): Likewise. (FCVT_F2FIXED): Likewise.
(fcvt_fixed_insn): New define_int_attr. (fcvt_fixed_insn): New define_int_attr.
2016-06-07 Jan Hubicka <hubicka@ucw.cz> 2016-06-07 Jan Hubicka <hubicka@ucw.cz>
......
gcc/config/aarch64/aarch64-simd-builtins.def
...@@ -447,7 +447,7 @@ ...@@ -447,7 +447,7 @@
BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0) BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0)
/* Implemented by <FCVT_F2FIXED/FIXED2F:fcvt_fixed_insn><*><*>3. */ /* Implemented by <FCVT_F2FIXED/FIXED2F:fcvt_fixed_insn><*><*>3. */
BUILTIN_GPI (BINOP, scvtf, 3) BUILTIN_VSDQ_SDI (BINOP, scvtf, 3)
BUILTIN_GPI (BINOP_SUS, ucvtf, 3) BUILTIN_VSDQ_SDI (BINOP_SUS, ucvtf, 3)
BUILTIN_GPF (BINOP, fcvtzs, 3) BUILTIN_VALLF (BINOP, fcvtzs, 3)
BUILTIN_GPF (BINOP_USS, fcvtzu, 3) BUILTIN_VALLF (BINOP_USS, fcvtzu, 3)
gcc/config/aarch64/aarch64-simd.md
...@@ -1778,6 +1778,28 @@ ...@@ -1778,6 +1778,28 @@
[(set_attr "type" "neon_fp_cvt_widen_s")] [(set_attr "type" "neon_fp_cvt_widen_s")]
) )
;; Convert between fixed-point and floating-point (vector modes)
(define_insn "<FCVT_F2FIXED:fcvt_fixed_insn><VDQF:mode>3"
[(set (match_operand:<VDQF:FCVT_TARGET> 0 "register_operand" "=w")
(unspec:<VDQF:FCVT_TARGET> [(match_operand:VDQF 1 "register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i")]
FCVT_F2FIXED))]
"TARGET_SIMD"
"<FCVT_F2FIXED:fcvt_fixed_insn>\t%<v>0<Vmtype>, %<v>1<Vmtype>, #%2"
[(set_attr "type" "neon_fp_to_int_<VDQF:Vetype><q>")]
)
(define_insn "<FCVT_FIXED2F:fcvt_fixed_insn><VDQ_SDI:mode>3"
[(set (match_operand:<VDQ_SDI:FCVT_TARGET> 0 "register_operand" "=w")
(unspec:<VDQ_SDI:FCVT_TARGET> [(match_operand:VDQ_SDI 1 "register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i")]
FCVT_FIXED2F))]
"TARGET_SIMD"
"<FCVT_FIXED2F:fcvt_fixed_insn>\t%<v>0<Vmtype>, %<v>1<Vmtype>, #%2"
[(set_attr "type" "neon_int_to_fp_<VDQ_SDI:Vetype><q>")]
)
;; ??? Note that the vectorizer usage of the vec_unpacks_[lo/hi] patterns ;; ??? Note that the vectorizer usage of the vec_unpacks_[lo/hi] patterns
;; is inconsistent with vector ordering elsewhere in the compiler, in that ;; is inconsistent with vector ordering elsewhere in the compiler, in that
;; the meaning of HI and LO changes depending on the target endianness. ;; the meaning of HI and LO changes depending on the target endianness.
......
gcc/config/aarch64/iterators.md
...@@ -154,6 +154,12 @@ ...@@ -154,6 +154,12 @@
;; Vector modes for S type. ;; Vector modes for S type.
(define_mode_iterator VDQ_SI [V2SI V4SI]) (define_mode_iterator VDQ_SI [V2SI V4SI])
;; Vector modes for S and D
(define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
;; Scalar and Vector modes for S and D
(define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
;; Vector modes for Q and H types. ;; Vector modes for Q and H types.
(define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI]) (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
...@@ -649,8 +655,10 @@ ...@@ -649,8 +655,10 @@
[(QI "b") (HI "h") (SI "") (DI "")]) [(QI "b") (HI "h") (SI "") (DI "")])
(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si") (define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
(V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
(SF "si") (DF "di") (SI "sf") (DI "df")]) (SF "si") (DF "di") (SI "sf") (DI "df")])
(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI") (define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
(V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
(SF "SI") (DF "DI") (SI "SF") (DI "DF")]) (SF "SI") (DF "DI") (SI "SF") (DI "DF")])
......
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