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riscv-gcc-1
Commit 264159d2 by Kito Cheng Committed by Chung-Ju Wu
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[NDS32] Add load_multiple,store_multiple and new attribute combo. 

gcc/
	* config/nds32/nds32.md (type): Add load_multiple and store_multiple.
	(combo): New attribute.
	* config/nds32/nds32-multiple.md: Refine patterns with new attributes.

Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com>

From-SVN: r258232
parent 38946ea1
Showing with 58 additions and 31 deletions
gcc/ChangeLog
2018-03-04 Kito Cheng <kito.cheng@gmail.com>
Chung-Ju Wu <jasonwucj@gmail.com>
* config/nds32/nds32.md (type): Add load_multiple and store_multiple.
(combo): New attribute.
* config/nds32/nds32-multiple.md: Refine patterns with new attributes.
2018-03-03 Chung-Ju Wu <jasonwucj@gmail.com> 2018-03-03 Chung-Ju Wu <jasonwucj@gmail.com>
* config/nds32/nds32.opt: Change -mcmodel= default value. * config/nds32/nds32.opt: Change -mcmodel= default value.
......
gcc/config/nds32/nds32-multiple.md
...@@ -96,8 +96,9 @@ ...@@ -96,8 +96,9 @@
(mem:SI (plus:SI (match_dup 1) (const_int 28))))])] (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
"(XVECLEN (operands[0], 0) == 8)" "(XVECLEN (operands[0], 0) == 8)"
"lmw.bi\t%2, [%1], %9, 0x0" "lmw.bi\t%2, [%1], %9, 0x0"
[(set_attr "type" "load") [(set_attr "type" "load_multiple")
(set_attr "length" "4")] (set_attr "combo" "8")
(set_attr "length" "4")]
) )
(define_insn "*lmwsi7" (define_insn "*lmwsi7"
...@@ -118,8 +119,9 @@ ...@@ -118,8 +119,9 @@
(mem:SI (plus:SI (match_dup 1) (const_int 24))))])] (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
"(XVECLEN (operands[0], 0) == 7)" "(XVECLEN (operands[0], 0) == 7)"
"lmw.bi\t%2, [%1], %8, 0x0" "lmw.bi\t%2, [%1], %8, 0x0"
[(set_attr "type" "load") [(set_attr "type" "load_multiple")
(set_attr "length" "4")] (set_attr "combo" "7")
(set_attr "length" "4")]
) )
(define_insn "*lmwsi6" (define_insn "*lmwsi6"
...@@ -138,8 +140,9 @@ ...@@ -138,8 +140,9 @@
(mem:SI (plus:SI (match_dup 1) (const_int 20))))])] (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
"(XVECLEN (operands[0], 0) == 6)" "(XVECLEN (operands[0], 0) == 6)"
"lmw.bi\t%2, [%1], %7, 0x0" "lmw.bi\t%2, [%1], %7, 0x0"
[(set_attr "type" "load") [(set_attr "type" "load_multiple")
(set_attr "length" "4")] (set_attr "combo" "6")
(set_attr "length" "4")]
) )
(define_insn "*lmwsi5" (define_insn "*lmwsi5"
...@@ -156,8 +159,9 @@ ...@@ -156,8 +159,9 @@
(mem:SI (plus:SI (match_dup 1) (const_int 16))))])] (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
"(XVECLEN (operands[0], 0) == 5)" "(XVECLEN (operands[0], 0) == 5)"
"lmw.bi\t%2, [%1], %6, 0x0" "lmw.bi\t%2, [%1], %6, 0x0"
[(set_attr "type" "load") [(set_attr "type" "load_multiple")
(set_attr "length" "4")] (set_attr "combo" "5")
(set_attr "length" "4")]
) )
(define_insn "*lmwsi4" (define_insn "*lmwsi4"
...@@ -172,8 +176,9 @@ ...@@ -172,8 +176,9 @@
(mem:SI (plus:SI (match_dup 1) (const_int 12))))])] (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
"(XVECLEN (operands[0], 0) == 4)" "(XVECLEN (operands[0], 0) == 4)"
"lmw.bi\t%2, [%1], %5, 0x0" "lmw.bi\t%2, [%1], %5, 0x0"
[(set_attr "type" "load") [(set_attr "type" "load_multiple")
(set_attr "length" "4")] (set_attr "combo" "4")
(set_attr "length" "4")]
) )
(define_insn "*lmwsi3" (define_insn "*lmwsi3"
...@@ -186,8 +191,9 @@ ...@@ -186,8 +191,9 @@
(mem:SI (plus:SI (match_dup 1) (const_int 8))))])] (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
"(XVECLEN (operands[0], 0) == 3)" "(XVECLEN (operands[0], 0) == 3)"
"lmw.bi\t%2, [%1], %4, 0x0" "lmw.bi\t%2, [%1], %4, 0x0"
[(set_attr "type" "load") [(set_attr "type" "load_multiple")
(set_attr "length" "4")] (set_attr "combo" "3")
(set_attr "length" "4")]
) )
(define_insn "*lmwsi2" (define_insn "*lmwsi2"
...@@ -198,8 +204,9 @@ ...@@ -198,8 +204,9 @@
(mem:SI (plus:SI (match_dup 1) (const_int 4))))])] (mem:SI (plus:SI (match_dup 1) (const_int 4))))])]
"(XVECLEN (operands[0], 0) == 2)" "(XVECLEN (operands[0], 0) == 2)"
"lmw.bi\t%2, [%1], %3, 0x0" "lmw.bi\t%2, [%1], %3, 0x0"
[(set_attr "type" "load") [(set_attr "type" "load_multiple")
(set_attr "length" "4")] (set_attr "combo" "2")
(set_attr "length" "4")]
) )
...@@ -280,8 +287,9 @@ ...@@ -280,8 +287,9 @@
(match_operand:SI 9 "register_operand" ""))])] (match_operand:SI 9 "register_operand" ""))])]
"(XVECLEN (operands[0], 0) == 8)" "(XVECLEN (operands[0], 0) == 8)"
"smw.bi\t%2, [%1], %9, 0x0" "smw.bi\t%2, [%1], %9, 0x0"
[(set_attr "type" "store") [(set_attr "type" "store_multiple")
(set_attr "length" "4")] (set_attr "combo" "8")
(set_attr "length" "4")]
) )
(define_insn "*stmsi7" (define_insn "*stmsi7"
...@@ -302,8 +310,9 @@ ...@@ -302,8 +310,9 @@
(match_operand:SI 8 "register_operand" ""))])] (match_operand:SI 8 "register_operand" ""))])]
"(XVECLEN (operands[0], 0) == 7)" "(XVECLEN (operands[0], 0) == 7)"
"smw.bi\t%2, [%1], %8, 0x0" "smw.bi\t%2, [%1], %8, 0x0"
[(set_attr "type" "store") [(set_attr "type" "store_multiple")
(set_attr "length" "4")] (set_attr "combo" "7")
(set_attr "length" "4")]
) )
(define_insn "*stmsi6" (define_insn "*stmsi6"
...@@ -322,8 +331,9 @@ ...@@ -322,8 +331,9 @@
(match_operand:SI 7 "register_operand" ""))])] (match_operand:SI 7 "register_operand" ""))])]
"(XVECLEN (operands[0], 0) == 6)" "(XVECLEN (operands[0], 0) == 6)"
"smw.bi\t%2, [%1], %7, 0x0" "smw.bi\t%2, [%1], %7, 0x0"
[(set_attr "type" "store") [(set_attr "type" "store_multiple")
(set_attr "length" "4")] (set_attr "combo" "6")
(set_attr "length" "4")]
) )
(define_insn "*stmsi5" (define_insn "*stmsi5"
...@@ -340,8 +350,9 @@ ...@@ -340,8 +350,9 @@
(match_operand:SI 6 "register_operand" ""))])] (match_operand:SI 6 "register_operand" ""))])]
"(XVECLEN (operands[0], 0) == 5)" "(XVECLEN (operands[0], 0) == 5)"
"smw.bi\t%2, [%1], %6, 0x0" "smw.bi\t%2, [%1], %6, 0x0"
[(set_attr "type" "store") [(set_attr "type" "store_multiple")
(set_attr "length" "4")] (set_attr "combo" "5")
(set_attr "length" "4")]
) )
(define_insn "*stmsi4" (define_insn "*stmsi4"
...@@ -356,8 +367,9 @@ ...@@ -356,8 +367,9 @@
(match_operand:SI 5 "register_operand" ""))])] (match_operand:SI 5 "register_operand" ""))])]
"(XVECLEN (operands[0], 0) == 4)" "(XVECLEN (operands[0], 0) == 4)"
"smw.bi\t%2, [%1], %5, 0x0" "smw.bi\t%2, [%1], %5, 0x0"
[(set_attr "type" "store") [(set_attr "type" "store_multiple")
(set_attr "length" "4")] (set_attr "combo" "4")
(set_attr "length" "4")]
) )
(define_insn "*stmsi3" (define_insn "*stmsi3"
...@@ -370,8 +382,9 @@ ...@@ -370,8 +382,9 @@
(match_operand:SI 4 "register_operand" ""))])] (match_operand:SI 4 "register_operand" ""))])]
"(XVECLEN (operands[0], 0) == 3)" "(XVECLEN (operands[0], 0) == 3)"
"smw.bi\t%2, [%1], %4, 0x0" "smw.bi\t%2, [%1], %4, 0x0"
[(set_attr "type" "store") [(set_attr "type" "store_multiple")
(set_attr "length" "4")] (set_attr "combo" "3")
(set_attr "length" "4")]
) )
(define_insn "*stmsi2" (define_insn "*stmsi2"
...@@ -382,8 +395,9 @@ ...@@ -382,8 +395,9 @@
(match_operand:SI 3 "register_operand" ""))])] (match_operand:SI 3 "register_operand" ""))])]
"(XVECLEN (operands[0], 0) == 2)" "(XVECLEN (operands[0], 0) == 2)"
"smw.bi\t%2, [%1], %3, 0x0" "smw.bi\t%2, [%1], %3, 0x0"
[(set_attr "type" "store") [(set_attr "type" "store_multiple")
(set_attr "length" "4")] (set_attr "combo" "2")
(set_attr "length" "4")]
) )
;; Move a block of memory if it is word aligned and MORE than 2 words long. ;; Move a block of memory if it is word aligned and MORE than 2 words long.
......
gcc/config/nds32/nds32.md
...@@ -52,13 +52,17 @@ ...@@ -52,13 +52,17 @@
;; Insn type, it is used to default other attribute values. ;; Insn type, it is used to default other attribute values.
(define_attr "type" (define_attr "type"
"unknown,move,load,store,alu,compare,branch,call,misc" "unknown,move,load,store,load_multiple,store_multiple,alu,compare,branch,call,misc"
(const_string "unknown")) (const_string "unknown"))
;; Length, in bytes, default is 4-bytes. ;; Length, in bytes, default is 4-bytes.
(define_attr "length" "" (const_int 4)) (define_attr "length" "" (const_int 4))
;; Indicate the amount of micro instructions.
(define_attr "combo"
"0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25"
(const_string "1"))
;; Enabled, which is used to enable/disable insn alternatives. ;; Enabled, which is used to enable/disable insn alternatives.
;; Note that we use length and TARGET_16_BIT here as criteria. ;; Note that we use length and TARGET_16_BIT here as criteria.
...@@ -2166,7 +2170,8 @@ create_template: ...@@ -2166,7 +2170,8 @@ create_template:
{ {
return nds32_output_stack_push (operands[0]); return nds32_output_stack_push (operands[0]);
} }
[(set_attr "type" "misc") [(set_attr "type" "store_multiple")
(set_attr "combo" "12")
(set_attr "enabled" "1") (set_attr "enabled" "1")
(set (attr "length") (set (attr "length")
(if_then_else (match_test "TARGET_V3PUSH (if_then_else (match_test "TARGET_V3PUSH
...@@ -2188,7 +2193,8 @@ create_template: ...@@ -2188,7 +2193,8 @@ create_template:
{ {
return nds32_output_stack_pop (operands[0]); return nds32_output_stack_pop (operands[0]);
} }
[(set_attr "type" "misc") [(set_attr "type" "load_multiple")
(set_attr "combo" "12")
(set_attr "enabled" "1") (set_attr "enabled" "1")
(set (attr "length") (set (attr "length")
(if_then_else (match_test "TARGET_V3PUSH (if_then_else (match_test "TARGET_V3PUSH
......
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