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riscv-gcc-1
Commit 2542ef05 by Richard Henderson Committed by Richard Henderson
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s390: Add mode attribute for mode bitsize 

        * config/s390/s390.md (bitsize): New mode attr.
        (*extzv<GPR>, *extzv<GPR>, *insv<GPR>_zEC12, *insv<GPR>_z10): Use it.
        (extend<HQI><DSI>2, zero_extend<HQI>si2): Likewise.
        (zero_extend<HQI>di2, fixuns_trunc<BFP><GPR>2): Likewise.

Co-Authored-By: Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

From-SVN: r194643
parent e3140518
Showing with 31 additions and 46 deletions
gcc/ChangeLog
...@@ -16,6 +16,11 @@ ...@@ -16,6 +16,11 @@
(*anddi3_cconly, *anddi3): Likewise. (*anddi3_cconly, *anddi3): Likewise.
(*andsi3, *andsi3_cconly, *andsi3_zarch): Likewise. (*andsi3, *andsi3_cconly, *andsi3_zarch): Likewise.
* config/s390/s390.md (bitsize): New mode attr.
(*extzv<GPR>, *extzv<GPR>, *insv<GPR>_zEC12, *insv<GPR>_z10): Use it.
(extend<HQI><DSI>2, zero_extend<HQI>si2): Likewise.
(zero_extend<HQI>di2, fixuns_trunc<BFP><GPR>2): Likewise.
2012-12-20 Thomas Schwinge <thomas@codesourcery.com> 2012-12-20 Thomas Schwinge <thomas@codesourcery.com>
PR bootstrap/55202 PR bootstrap/55202
gcc/config/s390/s390.md
...@@ -531,6 +531,9 @@ ...@@ -531,6 +531,9 @@
(define_mode_attr bfstart [(DI "s") (SI "t")]) (define_mode_attr bfstart [(DI "s") (SI "t")])
(define_mode_attr bfend [(DI "e") (SI "f")]) (define_mode_attr bfend [(DI "e") (SI "f")])
;; In place of GET_MODE_BITSIZE (<MODE>mode)
(define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
;; ;;
;;- Compare instructions. ;;- Compare instructions.
;; ;;
...@@ -3326,7 +3329,7 @@ ...@@ -3326,7 +3329,7 @@
operands[1] = adjust_address (operands[1], BLKmode, 0); operands[1] = adjust_address (operands[1], BLKmode, 0);
set_mem_size (operands[1], size); set_mem_size (operands[1], size);
operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
operands[3] = GEN_INT (mask); operands[3] = GEN_INT (mask);
}) })
...@@ -3353,7 +3356,7 @@ ...@@ -3353,7 +3356,7 @@
operands[1] = adjust_address (operands[1], BLKmode, 0); operands[1] = adjust_address (operands[1], BLKmode, 0);
set_mem_size (operands[1], size); set_mem_size (operands[1], size);
operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
operands[3] = GEN_INT (mask); operands[3] = GEN_INT (mask);
}) })
...@@ -3373,49 +3376,29 @@ ...@@ -3373,49 +3376,29 @@
FAIL; FAIL;
}) })
; The normal RTL expansion will never generate a zero_extract where
; the location operand isn't word mode. However, we do this in the
; back-end when generating atomic operations. See s390_two_part_insv.
(define_insn "*insv<mode>_zEC12" (define_insn "*insv<mode>_zEC12"
[(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
(match_operand 1 "const_int_operand" "I") (match_operand 1 "const_int_operand" "I") ; size
(match_operand 2 "const_int_operand" "I")) (match_operand 2 "const_int_operand" "I")) ; pos
(match_operand:GPR 3 "nonimmediate_operand" "d"))] (match_operand:GPR 3 "nonimmediate_operand" "d"))]
"TARGET_ZEC12 "TARGET_ZEC12
&& (INTVAL (operands[1]) + INTVAL (operands[2])) <= && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
GET_MODE_BITSIZE (<MODE>mode)" "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
{
int start = INTVAL (operands[2]);
int size = INTVAL (operands[1]);
int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
operands[2] = GEN_INT (offset + start); /* start bit position */
operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
start - size); /* left shift count */
return "risbgn\t%0,%3,%b2,%b1,%b4";
}
[(set_attr "op_type" "RIE")]) [(set_attr "op_type" "RIE")])
(define_insn "*insv<mode>_z10" (define_insn "*insv<mode>_z10"
[(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
(match_operand 1 "const_int_operand" "I") (match_operand 1 "const_int_operand" "I") ; size
(match_operand 2 "const_int_operand" "I")) (match_operand 2 "const_int_operand" "I")) ; pos
(match_operand:GPR 3 "nonimmediate_operand" "d")) (match_operand:GPR 3 "nonimmediate_operand" "d"))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_Z10 "TARGET_Z10
&& (INTVAL (operands[1]) + INTVAL (operands[2])) <= && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
GET_MODE_BITSIZE (<MODE>mode)" "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
{
int start = INTVAL (operands[2]);
int size = INTVAL (operands[1]);
int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
operands[2] = GEN_INT (offset + start); /* start bit position */
operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
start - size); /* left shift count */
return "risbg\t%0,%3,%b2,%b1,%b4";
}
[(set_attr "op_type" "RIE") [(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")]) (set_attr "z10prop" "z10_super_E1")])
...@@ -3585,8 +3568,7 @@ ...@@ -3585,8 +3568,7 @@
} }
else if (!TARGET_EXTIMM) else if (!TARGET_EXTIMM)
{ {
rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) - rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
GET_MODE_BITSIZE (<HQI:MODE>mode));
operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
...@@ -3688,8 +3670,7 @@ ...@@ -3688,8 +3670,7 @@
{ {
operands[1] = adjust_address (operands[1], BLKmode, 0); operands[1] = adjust_address (operands[1], BLKmode, 0);
set_mem_size (operands[1], GET_MODE_SIZE (QImode)); set_mem_size (operands[1], GET_MODE_SIZE (QImode));
operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
- GET_MODE_BITSIZE (QImode));
}) })
; ;
...@@ -3800,8 +3781,7 @@ ...@@ -3800,8 +3781,7 @@
} }
else if (!TARGET_EXTIMM) else if (!TARGET_EXTIMM)
{ {
rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
GET_MODE_BITSIZE(<MODE>mode));
operands[1] = gen_lowpart (DImode, operands[1]); operands[1] = gen_lowpart (DImode, operands[1]);
emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
...@@ -3818,7 +3798,7 @@ ...@@ -3818,7 +3798,7 @@
{ {
operands[1] = gen_lowpart (SImode, operands[1]); operands[1] = gen_lowpart (SImode, operands[1]);
emit_insn (gen_andsi3 (operands[0], operands[1], emit_insn (gen_andsi3 (operands[0], operands[1],
GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1))); GEN_INT ((1 << <HQI:bitsize>) - 1)));
DONE; DONE;
} }
}) })
...@@ -4011,8 +3991,8 @@ ...@@ -4011,8 +3991,8 @@
REAL_VALUE_TYPE cmp, sub; REAL_VALUE_TYPE cmp, sub;
operands[1] = force_reg (<BFP:MODE>mode, operands[1]); operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode); real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode); real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
emit_cmp_and_jump_insns (operands[1], emit_cmp_and_jump_insns (operands[1],
CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode), CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
...@@ -4727,9 +4707,9 @@ ...@@ -4727,9 +4707,9 @@
(plus:GPR (match_dup 1) (match_dup 2)))] (plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCAmode) "s390_match_ccmode (insn, CCAmode)
&& (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
|| CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
|| CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\")) /* Avoid INT32_MIN on 32 bit. */
&& INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))" && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
"@ "@
a<g>hi\t%0,%h2 a<g>hi\t%0,%h2
a<g>hik\t%0,%1,%h2 a<g>hik\t%0,%1,%h2
......
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