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riscv-gcc-1
Commit 24cdff34 by Bernd Schmidt Committed by Bernd Schmidt
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Revert an incorrect change 

From-SVN: r42262
parent 5a2c9d70
Showing with 13 additions and 6 deletions
gcc/ChangeLog
2001-05-18 Bernd Schmidt <bernds@redhat.com>
Revert
2001-02-09 Nick Clifton <nickc@redhat.com>
* config/arm/arm.md: Change output constraint on post inc
load/store multiple patterns to be a read/write constraint.
2001-05-18 Mark Mitchell <mark@codesourcery.com> 2001-05-18 Mark Mitchell <mark@codesourcery.com>
* function.c (expand_function_start): Avoid creating BLKmode * function.c (expand_function_start): Avoid creating BLKmode
......
gcc/config/arm/arm.md
...@@ -5239,7 +5239,7 @@ ...@@ -5239,7 +5239,7 @@
(define_insn "*ldmsi_postinc4" (define_insn "*ldmsi_postinc4"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "s_register_operand" "+r") [(set (match_operand:SI 1 "s_register_operand" "=r")
(plus:SI (match_operand:SI 2 "s_register_operand" "1") (plus:SI (match_operand:SI 2 "s_register_operand" "1")
(const_int 16))) (const_int 16)))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_register_operand" "")
...@@ -5258,7 +5258,7 @@ ...@@ -5258,7 +5258,7 @@
(define_insn "*ldmsi_postinc3" (define_insn "*ldmsi_postinc3"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "s_register_operand" "+r") [(set (match_operand:SI 1 "s_register_operand" "=r")
(plus:SI (match_operand:SI 2 "s_register_operand" "1") (plus:SI (match_operand:SI 2 "s_register_operand" "1")
(const_int 12))) (const_int 12)))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_register_operand" "")
...@@ -5275,7 +5275,7 @@ ...@@ -5275,7 +5275,7 @@
(define_insn "*ldmsi_postinc2" (define_insn "*ldmsi_postinc2"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "s_register_operand" "+r") [(set (match_operand:SI 1 "s_register_operand" "=r")
(plus:SI (match_operand:SI 2 "s_register_operand" "1") (plus:SI (match_operand:SI 2 "s_register_operand" "1")
(const_int 8))) (const_int 8)))
(set (match_operand:SI 3 "arm_hard_register_operand" "") (set (match_operand:SI 3 "arm_hard_register_operand" "")
...@@ -5361,7 +5361,7 @@ ...@@ -5361,7 +5361,7 @@
(define_insn "*stmsi_postinc4" (define_insn "*stmsi_postinc4"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (match_operand:SI 1 "s_register_operand" "+r") [(set (match_operand:SI 1 "s_register_operand" "=r")
(plus:SI (match_operand:SI 2 "s_register_operand" "1") (plus:SI (match_operand:SI 2 "s_register_operand" "1")
(const_int 16))) (const_int 16)))
(set (mem:SI (match_dup 2)) (set (mem:SI (match_dup 2))
...@@ -5380,7 +5380,7 @@ ...@@ -5380,7 +5380,7 @@
(define_insn "*stmsi_postinc3" (define_insn "*stmsi_postinc3"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (match_operand:SI 1 "s_register_operand" "+r") [(set (match_operand:SI 1 "s_register_operand" "=r")
(plus:SI (match_operand:SI 2 "s_register_operand" "1") (plus:SI (match_operand:SI 2 "s_register_operand" "1")
(const_int 12))) (const_int 12)))
(set (mem:SI (match_dup 2)) (set (mem:SI (match_dup 2))
...@@ -5397,7 +5397,7 @@ ...@@ -5397,7 +5397,7 @@
(define_insn "*stmsi_postinc2" (define_insn "*stmsi_postinc2"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (match_operand:SI 1 "s_register_operand" "+r") [(set (match_operand:SI 1 "s_register_operand" "=r")
(plus:SI (match_operand:SI 2 "s_register_operand" "1") (plus:SI (match_operand:SI 2 "s_register_operand" "1")
(const_int 8))) (const_int 8)))
(set (mem:SI (match_dup 2)) (set (mem:SI (match_dup 2))
......
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