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lvzhengyang
riscv-gcc-1
Commits
247f726f
Commit
247f726f
authored
May 09, 2018
by
Andreas Schwab
Committed by
Andreas Schwab
May 09, 2018
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* gcc.target/aarch64/sve/vcond_6.c: Add missing brace.
From-SVN: r260082
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gcc/testsuite/ChangeLog
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247f726f
2018-05-09 Andreas Schwab <schwab@suse.de>
* gcc.target/aarch64/sve/vcond_6.c: Add missing brace.
2018-05-09 Richard Sandiford <richard.sandiford@linaro.org>
* gcc.target/aarch64/store_lane_spill_1.c: New test.
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gcc/testsuite/gcc.target/aarch64/sve/vcond_6.c
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247f726f
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@@ -54,5 +54,5 @@ TEST_ALL (LOOP)
and then use NOT, but the original BIC sequence is better. It's a fairly
niche failure though. We'd handle most other types of comparison by
using the inverse operation instead of a separate NOT. */
/* { dg-final { scan-assembler-times {\tbic\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 { xfail *-*-* } } */
/* { dg-final { scan-assembler-times {\tbic\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 { xfail *-*-* } }
}
*/
/* { dg-final { scan-assembler-times {\torn\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 } } */
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