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Commit 246cc060 by Christophe Lyon
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[AArch64] Fix vqtb[lx][234] on big-endian 

2015-11-06  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* config/aarch64/aarch64-simd-builtins.def: Update builtins
	tables: add tbl3v16qi, qtbl[34]*, tbx4v16qi, qtbx[34]*.
	* config/aarch64/aarch64-simd.md (aarch64_tbl3v8qi): Rename to...
	(aarch64_tbl3<mode>) ... this, which supports v16qi too.
	(aarch64_tbx4v8qi): Rename to...
	aarch64_tbx4<mode>): ... this.
	(aarch64_qtbl3<mode>): New pattern.
	(aarch64_qtbx3<mode>): New pattern.
	(aarch64_qtbl4<mode>): New pattern.
	(aarch64_qtbx4<mode>): New pattern.
	* config/aarch64/arm_neon.h (vqtbl2_s8, vqtbl2_u8, vqtbl2_p8)
	(vqtbl2q_s8, vqtbl2q_u8, vqtbl2q_p8, vqtbl3_s8, vqtbl3_u8)
	(vqtbl3_p8, vqtbl3q_s8, vqtbl3q_u8, vqtbl3q_p8, vqtbl4_s8)
	(vqtbl4_u8, vqtbl4_p8, vqtbl4q_s8, vqtbl4q_u8, vqtbl4q_p8)
	(vqtbx2_s8, vqtbx2_u8, vqtbx2_p8, vqtbx2q_s8, vqtbx2q_u8)
	(vqtbx2q_p8, vqtbx3_s8, vqtbx3_u8, vqtbx3_p8, vqtbx3q_s8)
	(vqtbx3q_u8, vqtbx3q_p8, vqtbx4_s8, vqtbx4_u8, vqtbx4_p8)
	(vqtbx4q_s8, vqtbx4q_u8, vqtbx4q_p8): Rewrite using builtin
	functions.

	gcc/testsuite/
	* gcc.target/aarch64/advsimd-intrinsics/vqtbX.c: New test.

From-SVN: r229886
parent a881fb0c
Showing with 103 additions and 13 deletions
gcc/ChangeLog
2015-11-06 Christophe Lyon <christophe.lyon@linaro.org>
* config/aarch64/aarch64-simd-builtins.def: Update builtins
tables: add tbl3v16qi, qtbl[34]*, tbx4v16qi, qtbx[34]*.
* config/aarch64/aarch64-simd.md (aarch64_tbl3v8qi): Rename to...
(aarch64_tbl3<mode>) ... this, which supports v16qi too.
(aarch64_tbx4v8qi): Rename to...
aarch64_tbx4<mode>): ... this.
(aarch64_qtbl3<mode>): New pattern.
(aarch64_qtbx3<mode>): New pattern.
(aarch64_qtbl4<mode>): New pattern.
(aarch64_qtbx4<mode>): New pattern.
* config/aarch64/arm_neon.h (vqtbl2_s8, vqtbl2_u8, vqtbl2_p8)
(vqtbl2q_s8, vqtbl2q_u8, vqtbl2q_p8, vqtbl3_s8, vqtbl3_u8)
(vqtbl3_p8, vqtbl3q_s8, vqtbl3q_u8, vqtbl3q_p8, vqtbl4_s8)
(vqtbl4_u8, vqtbl4_p8, vqtbl4q_s8, vqtbl4q_u8, vqtbl4q_p8)
(vqtbx2_s8, vqtbx2_u8, vqtbx2_p8, vqtbx2q_s8, vqtbx2q_u8)
(vqtbx2q_p8, vqtbx3_s8, vqtbx3_u8, vqtbx3_p8, vqtbx3q_s8)
(vqtbx3q_u8, vqtbx3q_p8, vqtbx4_s8, vqtbx4_u8, vqtbx4_p8)
(vqtbx4q_s8, vqtbx4q_u8, vqtbx4q_p8): Rewrite using builtin
functions.
2015-11-06 Mike Stump <mikestump@comcast.net>
PR debug/66728
gcc/config/aarch64/aarch64-simd-builtins.def
......@@ -408,8 +408,26 @@
VAR1 (BINOPP, crypto_pmull, 0, di)
VAR1 (BINOPP, crypto_pmull, 0, v2di)
/* Implemented by aarch64_tbl3v8qi. */
/* Implemented by aarch64_tbl3<mode>. */
VAR1 (BINOP, tbl3, 0, v8qi)
VAR1 (BINOP, tbl3, 0, v16qi)
/* Implemented by aarch64_tbx4v8qi. */
/* Implemented by aarch64_qtbl3<mode>. */
VAR1 (BINOP, qtbl3, 0, v8qi)
VAR1 (BINOP, qtbl3, 0, v16qi)
/* Implemented by aarch64_qtbl4<mode>. */
VAR1 (BINOP, qtbl4, 0, v8qi)
VAR1 (BINOP, qtbl4, 0, v16qi)
/* Implemented by aarch64_tbx4<mode>. */
VAR1 (TERNOP, tbx4, 0, v8qi)
VAR1 (TERNOP, tbx4, 0, v16qi)
/* Implemented by aarch64_qtbx3<mode>. */
VAR1 (TERNOP, qtbx3, 0, v8qi)
VAR1 (TERNOP, qtbx3, 0, v16qi)
/* Implemented by aarch64_qtbx4<mode>. */
VAR1 (TERNOP, qtbx4, 0, v8qi)
VAR1 (TERNOP, qtbx4, 0, v16qi)
gcc/config/aarch64/aarch64-simd.md
......@@ -4816,24 +4816,70 @@
[(set_attr "type" "neon_tbl2_q")]
)
(define_insn "aarch64_tbl3v8qi"
[(set (match_operand:V8QI 0 "register_operand" "=w")
(unspec:V8QI [(match_operand:OI 1 "register_operand" "w")
(match_operand:V8QI 2 "register_operand" "w")]
(define_insn "aarch64_tbl3<mode>"
[(set (match_operand:VB 0 "register_operand" "=w")
(unspec:VB [(match_operand:OI 1 "register_operand" "w")
(match_operand:VB 2 "register_operand" "w")]
UNSPEC_TBL))]
"TARGET_SIMD"
"tbl\\t%S0.8b, {%S1.16b - %T1.16b}, %S2.8b"
"tbl\\t%S0.<Vbtype>, {%S1.16b - %T1.16b}, %S2.<Vbtype>"
[(set_attr "type" "neon_tbl3")]
)
(define_insn "aarch64_tbx4v8qi"
[(set (match_operand:V8QI 0 "register_operand" "=w")
(unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0")
(define_insn "aarch64_tbx4<mode>"
[(set (match_operand:VB 0 "register_operand" "=w")
(unspec:VB [(match_operand:VB 1 "register_operand" "0")
(match_operand:OI 2 "register_operand" "w")
(match_operand:V8QI 3 "register_operand" "w")]
(match_operand:VB 3 "register_operand" "w")]
UNSPEC_TBX))]
"TARGET_SIMD"
"tbx\\t%S0.<Vbtype>, {%S2.16b - %T2.16b}, %S3.<Vbtype>"
[(set_attr "type" "neon_tbl4")]
)
;; Three source registers.
(define_insn "aarch64_qtbl3<mode>"
[(set (match_operand:VB 0 "register_operand" "=w")
(unspec:VB [(match_operand:CI 1 "register_operand" "w")
(match_operand:VB 2 "register_operand" "w")]
UNSPEC_TBL))]
"TARGET_SIMD"
"tbl\\t%S0.<Vbtype>, {%S1.16b - %U1.16b}, %S2.<Vbtype>"
[(set_attr "type" "neon_tbl3")]
)
(define_insn "aarch64_qtbx3<mode>"
[(set (match_operand:VB 0 "register_operand" "=w")
(unspec:VB [(match_operand:VB 1 "register_operand" "0")
(match_operand:CI 2 "register_operand" "w")
(match_operand:VB 3 "register_operand" "w")]
UNSPEC_TBX))]
"TARGET_SIMD"
"tbx\\t%S0.<Vbtype>, {%S2.16b - %U2.16b}, %S3.<Vbtype>"
[(set_attr "type" "neon_tbl3")]
)
;; Four source registers.
(define_insn "aarch64_qtbl4<mode>"
[(set (match_operand:VB 0 "register_operand" "=w")
(unspec:VB [(match_operand:XI 1 "register_operand" "w")
(match_operand:VB 2 "register_operand" "w")]
UNSPEC_TBL))]
"TARGET_SIMD"
"tbl\\t%S0.<Vbtype>, {%S1.16b - %V1.16b}, %S2.<Vbtype>"
[(set_attr "type" "neon_tbl4")]
)
(define_insn "aarch64_qtbx4<mode>"
[(set (match_operand:VB 0 "register_operand" "=w")
(unspec:VB [(match_operand:VB 1 "register_operand" "0")
(match_operand:XI 2 "register_operand" "w")
(match_operand:VB 3 "register_operand" "w")]
UNSPEC_TBX))]
"TARGET_SIMD"
"tbx\\t%S0.8b, {%S2.16b - %T2.16b}, %S3.8b"
"tbx\\t%S0.<Vbtype>, {%S2.16b - %V2.16b}, %S3.<Vbtype>"
[(set_attr "type" "neon_tbl4")]
)
......
gcc/testsuite/ChangeLog
2015-11-06 Christophe Lyon <christophe.lyon@linaro.org>
* gcc.target/aarch64/advsimd-intrinsics/vqtbX.c: New test.
2015-11-06 David Malcolm <dmalcolm@redhat.com>
* gcc.dg/plugin/diagnostic-test-show-locus-bw.c: New file.
......@@ -17,7 +21,7 @@
* gfortran.dg/goacc/combined_loop.f90: XFAIL.
2015-11-07 Jan Hubicka <hubicka@ucw.cz>
2015-11-06 Jan Hubicka <hubicka@ucw.cz>
PR ipa/68057
PR ipa/68220
......
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