rs6000.h (rs6000_builtins): Add vsldoi variants.

        * config/rs6000/rs6000.h (rs6000_builtins): Add vsldoi variants.

        * config/rs6000/rs6000.md ("altivec_vsldoi_*"): Same.

        * config/rs6000/rs6000.c: Clean up some spacing and indentation.
        (altivec_init_builtins): Add tree types for builtins with 4 bit
        literals.
	(bdesc_3arg): Add vsldoi variants.

From-SVN: r48282

gcc/ChangeLog

+2001-12-22  Aldy Hernandez  <aldyh@redhat.com>
+
+        * config/rs6000/rs6000.h (rs6000_builtins): Add vsldoi variants.
+
+        * config/rs6000/rs6000.md ("altivec_vsldoi_*"): Same.
+
+        * config/rs6000/rs6000.c: Clean up some spacing and indentation.
+        (altivec_init_builtins): Add tree types for builtins with 4 bit
+        literals.
+	(bdesc_3arg): Add vsldoi variants.
+
 2001-12-22  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
 
 	* 1750a.h (datalbl, jmplbl): Declare array size explicitly.

gcc/config/rs6000/rs6000.h

@@ -2948,5 +2948,9 @@ enum rs6000_builtins
   ALTIVEC_BUILTIN_VSUM4SHS,
   ALTIVEC_BUILTIN_VSUM2SWS,
   ALTIVEC_BUILTIN_VSUMSWS,
-  ALTIVEC_BUILTIN_VXOR
+  ALTIVEC_BUILTIN_VXOR,
+  ALTIVEC_BUILTIN_VSLDOI_16QI,
+  ALTIVEC_BUILTIN_VSLDOI_8HI,
+  ALTIVEC_BUILTIN_VSLDOI_4SI,
+  ALTIVEC_BUILTIN_VSLDOI_4SF
 };

gcc/config/rs6000/rs6000.md

@@ -15191,4 +15191,38 @@
   "vsel %0,%1,%2,%3"
   [(set_attr "type" "vecperm")])
 
+(define_insn "altivec_vsldoi_4si"
+  [(set (match_operand:V4SI 0 "register_operand" "=v")
+        (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
+		      (match_operand:V4SI 2 "register_operand" "v")
+                      (match_operand:QI 3 "immediate_operand" "i")] 163))]
+  "TARGET_ALTIVEC"
+  "vsldoi %0, %1, %2, %3"
+  [(set_attr "type" "vecperm")])
+
+(define_insn "altivec_vsldoi_4sf"
+  [(set (match_operand:V4SF 0 "register_operand" "=v")
+        (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
+		      (match_operand:V4SF 2 "register_operand" "v")
+                      (match_operand:QI 3 "immediate_operand" "i")] 164))]
+  "TARGET_ALTIVEC"
+  "vsldoi %0, %1, %2, %3"
+  [(set_attr "type" "vecperm")])
 
+(define_insn "altivec_vsldoi_8hi"
+  [(set (match_operand:V8HI 0 "register_operand" "=v")
+        (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
+		      (match_operand:V8HI 2 "register_operand" "v")
+                      (match_operand:QI 3 "immediate_operand" "i")] 165))]
+  "TARGET_ALTIVEC"
+  "vsldoi %0, %1, %2, %3"
+  [(set_attr "type" "vecperm")])
+
+(define_insn "altivec_vsldoi_16qi"
+  [(set (match_operand:V16QI 0 "register_operand" "=v")
+        (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
+		       (match_operand:V16QI 2 "register_operand" "v")
+		       (match_operand:QI 3 "immediate_operand" "i")] 166))]
+  "TARGET_ALTIVEC"
+  "vsldoi %0, %1, %2, %3"
+  [(set_attr "type" "vecperm")])