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riscv-gcc-1
Commit 23902d70 by Uros Bizjak Committed by Uros Bizjak
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i386.md (*scc_bt<mode>): New insn_and_split pattern. 

	* config/i386/i386.md (*scc_bt<mode>): New insn_and_split pattern.
	(*scc_bt<mode>_1): Ditto.
	(*scc_bt<mode>_mask): Ditto.

testsuite/ChangeLog:

	* gcc.target/i386/bt-5.c: New test.
	* gcc.target/i386/bt-6.c: Ditto.
	* gcc.target/i386/bt-mask-3.c: Ditto.
	* gcc.target/i386/bt-mask-4.c: Ditto.

From-SVN: r252986
parent 14a1a59f
Showing with 152 additions and 0 deletions
gcc/ChangeLog
2017-09-19 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (*scc_bt<mode>): New insn_and_split pattern.
(*scc_bt<mode>_1): Ditto.
(*scc_bt<mode>_mask): Ditto.
2017-09-19 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.c (ix86_split_long_move): Do not handle
address used for LEA in a special way.
......
gcc/config/i386/i386.md
......@@ -11246,6 +11246,98 @@
(const_string "SI")
(const_string "<MODE>")))])
(define_insn_and_split "*scc_bt<mode>"
[(set (match_operand:QI 0 "nonimmediate_operand")
(match_operator 1 "bt_comparison_operator"
[(zero_extract:SWI48
(match_operand:SWI48 2 "nonimmediate_operand")
(const_int 1)
(match_operand:SI 3 "nonmemory_operand"))
(const_int 0)]))
(clobber (reg:CC FLAGS_REG))]
"(TARGET_USE_BT || optimize_function_for_size_p (cfun))
&& (CONST_INT_P (operands[3])
? (INTVAL (operands[3]) < GET_MODE_BITSIZE (<MODE>mode)
&& INTVAL (operands[3])
>= (optimize_function_for_size_p (cfun) ? 8 : 32))
: !memory_operand (operands[2], <MODE>mode))
&& can_create_pseudo_p ()"
"#"
"&& 1"
[(set (reg:CCC FLAGS_REG)
(compare:CCC
(zero_extract:SWI48
(match_dup 2)
(const_int 1)
(match_dup 3))
(const_int 0)))
(set (match_dup 0)
(match_op_dup 1 [(reg:CCC FLAGS_REG) (const_int 0)]))]
{
operands[1] = shallow_copy_rtx (operands[1]);
PUT_CODE (operands[1], reverse_condition (GET_CODE (operands[1])));
})
(define_insn_and_split "*scc_bt<mode>_1"
[(set (match_operand:QI 0 "nonimmediate_operand")
(match_operator 1 "bt_comparison_operator"
[(zero_extract:SWI48
(match_operand:SWI48 2 "register_operand")
(const_int 1)
(zero_extend:SI
(match_operand:QI 3 "register_operand")))
(const_int 0)]))
(clobber (reg:CC FLAGS_REG))]
"(TARGET_USE_BT || optimize_function_for_size_p (cfun))
&& can_create_pseudo_p ()"
"#"
"&& 1"
[(set (reg:CCC FLAGS_REG)
(compare:CCC
(zero_extract:SWI48
(match_dup 2)
(const_int 1)
(match_dup 3))
(const_int 0)))
(set (match_dup 0)
(match_op_dup 1 [(reg:CCC FLAGS_REG) (const_int 0)]))]
{
operands[3] = lowpart_subreg (SImode, operands[3], QImode);
operands[1] = shallow_copy_rtx (operands[1]);
PUT_CODE (operands[1], reverse_condition (GET_CODE (operands[1])));
})
;; Avoid useless masking of bit offset operand.
(define_insn_and_split "*scc_bt<mode>_mask"
[(set (match_operand:QI 0 "nonimmediate_operand")
(match_operator 1 "bt_comparison_operator"
[(zero_extract:SWI48
(match_operand:SWI48 2 "register_operand")
(const_int 1)
(and:SI
(match_operand:SI 3 "register_operand")
(match_operand 4 "const_int_operand")))]))
(clobber (reg:CC FLAGS_REG))]
"(TARGET_USE_BT || optimize_function_for_size_p (cfun))
&& (INTVAL (operands[4]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
== GET_MODE_BITSIZE (<MODE>mode)-1
&& can_create_pseudo_p ()"
"#"
"&& 1"
[(set (reg:CCC FLAGS_REG)
(compare:CCC
(zero_extract:SWI48
(match_dup 2)
(const_int 1)
(match_dup 3))
(const_int 0)))
(set (match_dup 0)
(match_op_dup 1 [(reg:CCC FLAGS_REG) (const_int 0)]))]
{
operands[1] = shallow_copy_rtx (operands[1]);
PUT_CODE (operands[1], reverse_condition (GET_CODE (operands[1])));
})
(define_insn_and_split "*jcc_bt<mode>"
[(set (pc)
(if_then_else (match_operator 0 "bt_comparison_operator"
......
gcc/testsuite/ChangeLog
2017-09-19 Uros Bizjak <ubizjak@gmail.com>
* gcc.target/i386/bt-5.c: New test.
* gcc.target/i386/bt-6.c: Ditto.
* gcc.target/i386/bt-mask-3.c: Ditto.
* gcc.target/i386/bt-mask-4.c: Ditto.
2017-09-19 Jakub Jelinek <jakub@redhat.com>
* g++.dg/tree-ssa/pr31146-2.C: Only do scan-tree-dump for c++14_down.
......
gcc/testsuite/gcc.target/i386/bt-5.c 0 → 100644
/* PR target/36473 */
/* { dg-do compile } */
/* { dg-options "-O2 -mtune=core2" } */
/* { dg-additional-options "-mregparm=2" { target ia32 } } */
int test(unsigned x, unsigned n)
{
return !(x & ( 0x01 << n ));
}
/* { dg-final { scan-assembler "btl\[ \t\]" } } */
gcc/testsuite/gcc.target/i386/bt-6.c 0 → 100644
/* PR target/36473 */
/* { dg-do compile } */
/* { dg-options "-O2 -mtune=core2" } */
/* { dg-additional-options "-mregparm=2" { target ia32 } } */
int test(unsigned long x, unsigned long n)
{
return !(x & ( (long)0x01 << n ));
}
/* { dg-final { scan-assembler "btl\[ \t\]" { target { ! lp64 } } } } */
/* { dg-final { scan-assembler "btq\[ \t\]" { target lp64 } } } */
gcc/testsuite/gcc.target/i386/bt-mask-3.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -mtune=core2" } */
/* { dg-additional-options "-mregparm=2" { target ia32 } } */
int test (unsigned x, unsigned n)
{
n &= 0x1f;
return !(x & (0x01 << n));
}
/* { dg-final { scan-assembler-not "and\[lq\]\[ \t\]" } } */
gcc/testsuite/gcc.target/i386/bt-mask-4.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -mtune=core2" } */
/* { dg-additional-options "-mregparm=2" { target ia32 } } */
int test (unsigned long x, unsigned long n)
{
n &= 0x3f;
return !(x & ((long)0x01 << n));
}
/* { dg-final { scan-assembler-not "and\[lq\]\[ \t\]" } } */
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