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riscv-gcc-1
Commit 2371eaec by Richard Henderson Committed by Richard Henderson
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rs6000: Rename patterns for vec_widen_<s>mult_even/odd_<mode> 

        * config/rs6000/altivec.md (vec_widen_umult_even_v16qi): Rename
        from altivec_vmuleub.
        (vec_widen_smult_even_v16qi): Rename from altivec_vmulesb.
        (vec_widen_umult_even_v8hi): Rename from altivec_vmuleuh.
        (vec_widen_smult_even_v8hi): Rename from altivec_vmulesh.
        (vec_widen_umult_odd_v16qi): Rename from altivec_vmuloub.
        (vec_widen_smult_odd_v16qi): Rename from altivec_vmulosb.
        (vec_widen_umult_odd_v8hi): Rename from altivec_vmulouh.
        (vec_widen_smult_odd_v8hi): Rename from altivec_vmulosh.
        * config/rs6000/rs6000-builtin.def: Update pattern names to match.

From-SVN: r189405
parent c6b37fab
Showing with 50 additions and 39 deletions
gcc/ChangeLog
2012-07-10 Richard Henderson <rth@redhat.com> 2012-07-10 Richard Henderson <rth@redhat.com>
* config/rs6000/altivec.md (vec_widen_umult_even_v16qi): Rename
from altivec_vmuleub.
(vec_widen_smult_even_v16qi): Rename from altivec_vmulesb.
(vec_widen_umult_even_v8hi): Rename from altivec_vmuleuh.
(vec_widen_smult_even_v8hi): Rename from altivec_vmulesh.
(vec_widen_umult_odd_v16qi): Rename from altivec_vmuloub.
(vec_widen_smult_odd_v16qi): Rename from altivec_vmulosb.
(vec_widen_umult_odd_v8hi): Rename from altivec_vmulouh.
(vec_widen_smult_odd_v8hi): Rename from altivec_vmulosh.
* config/rs6000/rs6000-builtin.def: Update pattern names to match.
* config/i386/sse.md (vec_widen_umult_even_v8si): Rename from * config/i386/sse.md (vec_widen_umult_even_v8si): Rename from
avx2_umulv4siv4di3. avx2_umulv4siv4di3.
(vec_widen_umult_even_v4si): Rename from sse2_umulv2siv2di3. (vec_widen_umult_even_v4si): Rename from sse2_umulv2siv2di3.
......
gcc/config/rs6000/altivec.md
...@@ -643,7 +643,7 @@ ...@@ -643,7 +643,7 @@
convert_move (small_swap, swap, 0); convert_move (small_swap, swap, 0);
low_product = gen_reg_rtx (V4SImode); low_product = gen_reg_rtx (V4SImode);
emit_insn (gen_altivec_vmulouh (low_product, one, two)); emit_insn (gen_vec_widen_umult_odd_v8hi (low_product, one, two));
high_product = gen_reg_rtx (V4SImode); high_product = gen_reg_rtx (V4SImode);
emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero)); emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));
...@@ -667,8 +667,8 @@ ...@@ -667,8 +667,8 @@
rtx high = gen_reg_rtx (V4SImode); rtx high = gen_reg_rtx (V4SImode);
rtx low = gen_reg_rtx (V4SImode); rtx low = gen_reg_rtx (V4SImode);
emit_insn (gen_altivec_vmulesh (even, operands[1], operands[2])); emit_insn (gen_vec_widen_smult_even_v8hi (even, operands[1], operands[2]));
emit_insn (gen_altivec_vmulosh (odd, operands[1], operands[2])); emit_insn (gen_vec_widen_smult_odd_v8hi (odd, operands[1], operands[2]));
emit_insn (gen_altivec_vmrghw (high, even, odd)); emit_insn (gen_altivec_vmrghw (high, even, odd));
emit_insn (gen_altivec_vmrglw (low, even, odd)); emit_insn (gen_altivec_vmrglw (low, even, odd));
...@@ -936,7 +936,7 @@ ...@@ -936,7 +936,7 @@
"vmrglw %0,%1,%2" "vmrglw %0,%1,%2"
[(set_attr "type" "vecperm")]) [(set_attr "type" "vecperm")])
(define_insn "altivec_vmuleub" (define_insn "vec_widen_umult_even_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v") [(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] (match_operand:V16QI 2 "register_operand" "v")]
...@@ -945,7 +945,7 @@ ...@@ -945,7 +945,7 @@
"vmuleub %0,%1,%2" "vmuleub %0,%1,%2"
[(set_attr "type" "veccomplex")]) [(set_attr "type" "veccomplex")])
(define_insn "altivec_vmulesb" (define_insn "vec_widen_smult_even_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v") [(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] (match_operand:V16QI 2 "register_operand" "v")]
...@@ -954,7 +954,7 @@ ...@@ -954,7 +954,7 @@
"vmulesb %0,%1,%2" "vmulesb %0,%1,%2"
[(set_attr "type" "veccomplex")]) [(set_attr "type" "veccomplex")])
(define_insn "altivec_vmuleuh" (define_insn "vec_widen_umult_even_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v") [(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] (match_operand:V8HI 2 "register_operand" "v")]
...@@ -963,7 +963,7 @@ ...@@ -963,7 +963,7 @@
"vmuleuh %0,%1,%2" "vmuleuh %0,%1,%2"
[(set_attr "type" "veccomplex")]) [(set_attr "type" "veccomplex")])
(define_insn "altivec_vmulesh" (define_insn "vec_widen_smult_even_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v") [(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] (match_operand:V8HI 2 "register_operand" "v")]
...@@ -972,7 +972,7 @@ ...@@ -972,7 +972,7 @@
"vmulesh %0,%1,%2" "vmulesh %0,%1,%2"
[(set_attr "type" "veccomplex")]) [(set_attr "type" "veccomplex")])
(define_insn "altivec_vmuloub" (define_insn "vec_widen_umult_odd_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v") [(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] (match_operand:V16QI 2 "register_operand" "v")]
...@@ -981,7 +981,7 @@ ...@@ -981,7 +981,7 @@
"vmuloub %0,%1,%2" "vmuloub %0,%1,%2"
[(set_attr "type" "veccomplex")]) [(set_attr "type" "veccomplex")])
(define_insn "altivec_vmulosb" (define_insn "vec_widen_smult_odd_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v") [(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] (match_operand:V16QI 2 "register_operand" "v")]
...@@ -990,7 +990,7 @@ ...@@ -990,7 +990,7 @@
"vmulosb %0,%1,%2" "vmulosb %0,%1,%2"
[(set_attr "type" "veccomplex")]) [(set_attr "type" "veccomplex")])
(define_insn "altivec_vmulouh" (define_insn "vec_widen_umult_odd_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v") [(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] (match_operand:V8HI 2 "register_operand" "v")]
...@@ -999,7 +999,7 @@ ...@@ -999,7 +999,7 @@
"vmulouh %0,%1,%2" "vmulouh %0,%1,%2"
[(set_attr "type" "veccomplex")]) [(set_attr "type" "veccomplex")])
(define_insn "altivec_vmulosh" (define_insn "vec_widen_smult_odd_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v") [(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] (match_operand:V8HI 2 "register_operand" "v")]
...@@ -2175,8 +2175,8 @@ ...@@ -2175,8 +2175,8 @@
rtx ve = gen_reg_rtx (V8HImode); rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode);
emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2])); emit_insn (gen_vec_widen_umult_even_v16qi (ve, operands[1], operands[2]));
emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2])); emit_insn (gen_vec_widen_umult_odd_v16qi (vo, operands[1], operands[2]));
emit_insn (gen_altivec_vmrghh (operands[0], ve, vo)); emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
DONE; DONE;
}") }")
...@@ -2192,8 +2192,8 @@ ...@@ -2192,8 +2192,8 @@
rtx ve = gen_reg_rtx (V8HImode); rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode);
emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2])); emit_insn (gen_vec_widen_umult_even_v16qi (ve, operands[1], operands[2]));
emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2])); emit_insn (gen_vec_widen_umult_odd_v16qi (vo, operands[1], operands[2]));
emit_insn (gen_altivec_vmrglh (operands[0], ve, vo)); emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
DONE; DONE;
}") }")
...@@ -2209,8 +2209,8 @@ ...@@ -2209,8 +2209,8 @@
rtx ve = gen_reg_rtx (V8HImode); rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode);
emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2])); emit_insn (gen_vec_widen_smult_even_v16qi (ve, operands[1], operands[2]));
emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2])); emit_insn (gen_vec_widen_smult_odd_v16qi (vo, operands[1], operands[2]));
emit_insn (gen_altivec_vmrghh (operands[0], ve, vo)); emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
DONE; DONE;
}") }")
...@@ -2226,8 +2226,8 @@ ...@@ -2226,8 +2226,8 @@
rtx ve = gen_reg_rtx (V8HImode); rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode);
emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2])); emit_insn (gen_vec_widen_smult_even_v16qi (ve, operands[1], operands[2]));
emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2])); emit_insn (gen_vec_widen_smult_odd_v16qi (vo, operands[1], operands[2]));
emit_insn (gen_altivec_vmrglh (operands[0], ve, vo)); emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
DONE; DONE;
}") }")
...@@ -2243,8 +2243,8 @@ ...@@ -2243,8 +2243,8 @@
rtx ve = gen_reg_rtx (V4SImode); rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode);
emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2])); emit_insn (gen_vec_widen_umult_even_v8hi (ve, operands[1], operands[2]));
emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2])); emit_insn (gen_vec_widen_umult_odd_v8hi (vo, operands[1], operands[2]));
emit_insn (gen_altivec_vmrghw (operands[0], ve, vo)); emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
DONE; DONE;
}") }")
...@@ -2260,8 +2260,8 @@ ...@@ -2260,8 +2260,8 @@
rtx ve = gen_reg_rtx (V4SImode); rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode);
emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2])); emit_insn (gen_vec_widen_umult_even_v8hi (ve, operands[1], operands[2]));
emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2])); emit_insn (gen_vec_widen_umult_odd_v8hi (vo, operands[1], operands[2]));
emit_insn (gen_altivec_vmrglw (operands[0], ve, vo)); emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
DONE; DONE;
}") }")
...@@ -2277,8 +2277,8 @@ ...@@ -2277,8 +2277,8 @@
rtx ve = gen_reg_rtx (V4SImode); rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode);
emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2])); emit_insn (gen_vec_widen_smult_even_v8hi (ve, operands[1], operands[2]));
emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2])); emit_insn (gen_vec_widen_smult_odd_v8hi (vo, operands[1], operands[2]));
emit_insn (gen_altivec_vmrghw (operands[0], ve, vo)); emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
DONE; DONE;
}") }")
...@@ -2294,8 +2294,8 @@ ...@@ -2294,8 +2294,8 @@
rtx ve = gen_reg_rtx (V4SImode); rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode);
emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2])); emit_insn (gen_vec_widen_smult_even_v8hi (ve, operands[1], operands[2]));
emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2])); emit_insn (gen_vec_widen_smult_odd_v8hi (vo, operands[1], operands[2]));
emit_insn (gen_altivec_vmrglw (operands[0], ve, vo)); emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
DONE; DONE;
}") }")
......
gcc/config/rs6000/rs6000-builtin.def
...@@ -503,18 +503,18 @@ BU_ALTIVEC_2 (VMINSH, "vminsh", CONST, sminv8hi3) ...@@ -503,18 +503,18 @@ BU_ALTIVEC_2 (VMINSH, "vminsh", CONST, sminv8hi3)
BU_ALTIVEC_2 (VMINUW, "vminuw", CONST, uminv4si3) BU_ALTIVEC_2 (VMINUW, "vminuw", CONST, uminv4si3)
BU_ALTIVEC_2 (VMINSW, "vminsw", CONST, sminv4si3) BU_ALTIVEC_2 (VMINSW, "vminsw", CONST, sminv4si3)
BU_ALTIVEC_2 (VMINFP, "vminfp", CONST, sminv4sf3) BU_ALTIVEC_2 (VMINFP, "vminfp", CONST, sminv4sf3)
BU_ALTIVEC_2 (VMULEUB, "vmuleub", CONST, altivec_vmuleub) BU_ALTIVEC_2 (VMULEUB, "vmuleub", CONST, vec_widen_umult_even_v16qi)
BU_ALTIVEC_2 (VMULEUB_UNS, "vmuleub_uns", CONST, altivec_vmuleub) BU_ALTIVEC_2 (VMULEUB_UNS, "vmuleub_uns", CONST, vec_widen_umult_even_v16qi)
BU_ALTIVEC_2 (VMULESB, "vmulesb", CONST, altivec_vmulesb) BU_ALTIVEC_2 (VMULESB, "vmulesb", CONST, vec_widen_smult_even_v16qi)
BU_ALTIVEC_2 (VMULEUH, "vmuleuh", CONST, altivec_vmuleuh) BU_ALTIVEC_2 (VMULEUH, "vmuleuh", CONST, vec_widen_umult_even_v8hi)
BU_ALTIVEC_2 (VMULEUH_UNS, "vmuleuh_uns", CONST, altivec_vmuleuh) BU_ALTIVEC_2 (VMULEUH_UNS, "vmuleuh_uns", CONST, vec_widen_umult_even_v8hi)
BU_ALTIVEC_2 (VMULESH, "vmulesh", CONST, altivec_vmulesh) BU_ALTIVEC_2 (VMULESH, "vmulesh", CONST, vec_widen_smult_even_v8hi)
BU_ALTIVEC_2 (VMULOUB, "vmuloub", CONST, altivec_vmuloub) BU_ALTIVEC_2 (VMULOUB, "vmuloub", CONST, vec_widen_umult_odd_v16qi)
BU_ALTIVEC_2 (VMULOUB_UNS, "vmuloub_uns", CONST, altivec_vmuloub) BU_ALTIVEC_2 (VMULOUB_UNS, "vmuloub_uns", CONST, vec_widen_umult_odd_v16qi)
BU_ALTIVEC_2 (VMULOSB, "vmulosb", CONST, altivec_vmulosb) BU_ALTIVEC_2 (VMULOSB, "vmulosb", CONST, vec_widen_smult_odd_v16qi)
BU_ALTIVEC_2 (VMULOUH, "vmulouh", CONST, altivec_vmulouh) BU_ALTIVEC_2 (VMULOUH, "vmulouh", CONST, vec_widen_umult_odd_v8hi)
BU_ALTIVEC_2 (VMULOUH_UNS, "vmulouh_uns", CONST, altivec_vmulouh) BU_ALTIVEC_2 (VMULOUH_UNS, "vmulouh_uns", CONST, vec_widen_umult_odd_v8hi)
BU_ALTIVEC_2 (VMULOSH, "vmulosh", CONST, altivec_vmulosh) BU_ALTIVEC_2 (VMULOSH, "vmulosh", CONST, vec_widen_smult_odd_v8hi)
BU_ALTIVEC_2 (VNOR, "vnor", CONST, norv4si3) BU_ALTIVEC_2 (VNOR, "vnor", CONST, norv4si3)
BU_ALTIVEC_2 (VOR, "vor", CONST, iorv4si3) BU_ALTIVEC_2 (VOR, "vor", CONST, iorv4si3)
BU_ALTIVEC_2 (VPKUHUM, "vpkuhum", CONST, altivec_vpkuhum) BU_ALTIVEC_2 (VPKUHUM, "vpkuhum", CONST, altivec_vpkuhum)
......
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