Commit 2359d013 by Richard Sandiford Committed by Richard Sandiford

mips.md (reload_outcc): Use HARD_REGNO_NREGS to access the second half of the…

mips.md (reload_outcc): Use HARD_REGNO_NREGS to access the second half of the TFmode scratch operand.

	* config/mips/mips.md (reload_outcc): Use HARD_REGNO_NREGS to
	access the second half of the TFmode scratch operand.

From-SVN: r44759
parent ca11a2e9
2001-08-10 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.md (reload_outcc): Use HARD_REGNO_NREGS to
access the second half of the TFmode scratch operand.
2001-08-10 Anthony Green <green@redhat.com> 2001-08-10 Anthony Green <green@redhat.com>
* java/class.c (emit_register_classes): Conditionalize code on * java/class.c (emit_register_classes): Conditionalize code on
......
...@@ -5667,6 +5667,7 @@ move\\t%0,%z4\\n\\ ...@@ -5667,6 +5667,7 @@ move\\t%0,%z4\\n\\
{ {
rtx source; rtx source;
rtx fp1, fp2; rtx fp1, fp2;
int regno;
/* This is called when are copying some value into a condition code /* This is called when are copying some value into a condition code
register. Operand 0 is the condition code register. Operand 1 register. Operand 0 is the condition code register. Operand 1
...@@ -5685,8 +5686,12 @@ move\\t%0,%z4\\n\\ ...@@ -5685,8 +5686,12 @@ move\\t%0,%z4\\n\\
else else
source = operands[1]; source = operands[1];
fp1 = gen_rtx_REG (SFmode, REGNO (operands[2])); /* FP1 and FP2 are the two halves of the TFmode scratch operand. They
fp2 = gen_rtx_REG (SFmode, REGNO (operands[2]) + 1); will be single registers in 64-bit mode and register pairs in 32-bit
mode. SOURCE is loaded into FP1 and zero is loaded into FP2. */
regno = REGNO (operands[2]);
fp1 = gen_rtx_REG (SFmode, regno);
fp2 = gen_rtx_REG (SFmode, regno + HARD_REGNO_NREGS (regno, DFmode));
emit_insn (gen_move_insn (fp1, source)); emit_insn (gen_move_insn (fp1, source));
emit_insn (gen_move_insn (fp2, gen_rtx_REG (SFmode, 0))); emit_insn (gen_move_insn (fp2, gen_rtx_REG (SFmode, 0)));
......
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