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Commit 230215f5 by Geoffrey Keating Committed by Geoffrey Keating
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[multiple changes] 

2005-04-29  Geoffrey Keating  <geoffk@apple.com>

	* config/rs6000/rs6000.md (floatsidf2_internal): Merge to create
	define_insn_and_split.  Split only when memory operand is
	offsettable.  Use adjust_address rather than plus_constant.
	(floatunssidf2_internal): Likewise.
	(fix_truncdfsi2_internal): Split only when memory operand is
	offsettable.  Use adjust_address rather than plus_constant.
	(fix_trunctfsi2_internal): Likewise.
	(floatsidf2_internal): Likewise.

Index: testsuite/ChangeLog
2005-05-02  Geoffrey Keating  <geoffk@apple.com>

	* gcc.dg/rs6000-fpint-2.c: New.

From-SVN: r99126
parent b565d777
Showing with 56 additions and 60 deletions
gcc/ChangeLog
2005-04-29 Geoffrey Keating <geoffk@apple.com>
PR target/20813
* config/rs6000/rs6000.md (floatsidf2_internal): Merge to create
define_insn_and_split. Split only when memory operand is
offsettable. Use adjust_address rather than plus_constant.
(floatunssidf2_internal): Likewise.
(fix_truncdfsi2_internal): Split only when memory operand is
offsettable. Use adjust_address rather than plus_constant.
(fix_trunctfsi2_internal): Likewise.
(floatsidf2_internal): Likewise.
2005-05-02 Diego Novillo <dnovillo@redhat.com> 2005-05-02 Diego Novillo <dnovillo@redhat.com>
* tree-vrp.c (set_value_range_to_nonnull): Declare inline. * tree-vrp.c (set_value_range_to_nonnull): Declare inline.
......
gcc/config/rs6000/rs6000.md
...@@ -5163,7 +5163,7 @@ ...@@ -5163,7 +5163,7 @@
operands[6] = gen_reg_rtx (SImode); operands[6] = gen_reg_rtx (SImode);
}") }")
(define_insn "*floatsidf2_internal" (define_insn_and_split "*floatsidf2_internal"
[(set (match_operand:DF 0 "gpc_reg_operand" "=&f") [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
(float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
(use (match_operand:SI 2 "gpc_reg_operand" "r")) (use (match_operand:SI 2 "gpc_reg_operand" "r"))
...@@ -5173,30 +5173,14 @@ ...@@ -5173,30 +5173,14 @@
(clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
"#" "#"
[(set_attr "length" "24")]) "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
[(pc)]
(define_split
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
(use (match_operand:SI 2 "gpc_reg_operand" ""))
(use (match_operand:DF 3 "gpc_reg_operand" ""))
(clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
(clobber (match_operand:DF 5 "gpc_reg_operand" ""))
(clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
(use (match_operand:SI 2 "gpc_reg_operand" ""))
(use (match_operand:DF 3 "gpc_reg_operand" ""))
(clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
(clobber (match_operand:DF 5 "gpc_reg_operand" ""))
(clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
" "
{ {
rtx lowword, highword; rtx lowword, highword;
gcc_assert (GET_CODE (operands[4]) == MEM); gcc_assert (MEM_P (operands[4]));
highword = XEXP (operands[4], 0); highword = adjust_address (operands[4], SImode, 0);
lowword = plus_constant (highword, 4); lowword = adjust_address (operands[4], SImode, 4);
if (! WORDS_BIG_ENDIAN) if (! WORDS_BIG_ENDIAN)
{ {
rtx tmp; rtx tmp;
...@@ -5205,12 +5189,13 @@ ...@@ -5205,12 +5189,13 @@
emit_insn (gen_xorsi3 (operands[6], operands[1], emit_insn (gen_xorsi3 (operands[6], operands[1],
GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); emit_move_insn (lowword, operands[6]);
emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); emit_move_insn (highword, operands[2]);
emit_move_insn (operands[5], operands[4]); emit_move_insn (operands[5], operands[4]);
emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
DONE; DONE;
}") }"
[(set_attr "length" "24")])
(define_expand "floatunssisf2" (define_expand "floatunssisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "") [(set (match_operand:SF 0 "gpc_reg_operand" "")
...@@ -5249,7 +5234,7 @@ ...@@ -5249,7 +5234,7 @@
operands[5] = gen_reg_rtx (DFmode); operands[5] = gen_reg_rtx (DFmode);
}") }")
(define_insn "*floatunssidf2_internal" (define_insn_and_split "*floatunssidf2_internal"
[(set (match_operand:DF 0 "gpc_reg_operand" "=&f") [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
(use (match_operand:SI 2 "gpc_reg_operand" "r")) (use (match_operand:SI 2 "gpc_reg_operand" "r"))
...@@ -5258,40 +5243,27 @@ ...@@ -5258,40 +5243,27 @@
(clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))] (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
"#" "#"
[(set_attr "length" "20")]) "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
[(pc)]
(define_split
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
(use (match_operand:SI 2 "gpc_reg_operand" ""))
(use (match_operand:DF 3 "gpc_reg_operand" ""))
(clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
(clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
(use (match_operand:SI 2 "gpc_reg_operand" ""))
(use (match_operand:DF 3 "gpc_reg_operand" ""))
(clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
(clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
" "
{ {
rtx lowword, highword; rtx lowword, highword;
gcc_assert (GET_CODE (operands[4]) == MEM); gcc_assert (MEM_P (operands[4]));
highword = XEXP (operands[4], 0); highword = adjust_address (operands[4], SImode, 0);
lowword = plus_constant (highword, 4); lowword = adjust_address (operands[4], SImode, 4);
if (! WORDS_BIG_ENDIAN) if (! WORDS_BIG_ENDIAN)
{ {
rtx tmp; rtx tmp;
tmp = highword; highword = lowword; lowword = tmp; tmp = highword; highword = lowword; lowword = tmp;
} }
emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]); emit_move_insn (lowword, operands[1]);
emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); emit_move_insn (highword, operands[2]);
emit_move_insn (operands[5], operands[4]); emit_move_insn (operands[5], operands[4]);
emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
DONE; DONE;
}") }"
[(set_attr "length" "20")])
; In the TARGET_PPC_GFXOPT case, this could and probably should ; In the TARGET_PPC_GFXOPT case, this could and probably should
; take a memory destination; but actually making this work is hard. ; take a memory destination; but actually making this work is hard.
...@@ -5331,19 +5303,17 @@ ...@@ -5331,19 +5303,17 @@
(clobber (match_operand:DI 3 "memory_operand" "=o"))] (clobber (match_operand:DI 3 "memory_operand" "=o"))]
"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
"#" "#"
"&& 1" "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
[(pc)] [(pc)]
" "
{ {
rtx lowword; rtx lowword;
gcc_assert (GET_CODE (operands[3]) == MEM); gcc_assert (MEM_P (operands[3]));
lowword = XEXP (operands[3], 0); lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
if (WORDS_BIG_ENDIAN)
lowword = plus_constant (lowword, 4);
emit_insn (gen_fctiwz (operands[2], operands[1])); emit_insn (gen_fctiwz (operands[2], operands[1]));
emit_move_insn (operands[3], operands[2]); emit_move_insn (operands[3], operands[2]);
emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); emit_move_insn (operands[0], lowword);
DONE; DONE;
}" }"
[(set_attr "length" "16")]) [(set_attr "length" "16")])
...@@ -8476,20 +8446,18 @@ ...@@ -8476,20 +8446,18 @@
"(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
"#" "#"
"&& reload_completed" "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
[(pc)] [(pc)]
{ {
rtx lowword; rtx lowword;
emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3])); emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
gcc_assert (GET_CODE (operands[5]) == MEM); gcc_assert (MEM_P (operands[5]));
lowword = XEXP (operands[5], 0); lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
if (WORDS_BIG_ENDIAN)
lowword = plus_constant (lowword, 4);
emit_insn (gen_fctiwz (operands[4], operands[2])); emit_insn (gen_fctiwz (operands[4], operands[2]));
emit_move_insn (operands[5], operands[4]); emit_move_insn (operands[5], operands[4]);
emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); emit_move_insn (operands[0], lowword);
DONE; DONE;
}) })
......
gcc/testsuite/ChangeLog
2005-05-02 Geoffrey Keating <geoffk@apple.com>
PR target/20813
* gcc.dg/rs6000-fpint-2.c: New.
2005-05-02 Joseph S. Myers <joseph@codesourcery.com> 2005-05-02 Joseph S. Myers <joseph@codesourcery.com>
PR c/15698 PR c/15698
......
gcc/testsuite/gcc.dg/rs6000-fpint-2.c 0 → 100644
/* { dg-do compile { target powerpc*-*-* rs6000-*-* } } */
/* { dg-options "-mno-powerpc-gfxopt -mpowerpc64" } */
extern void bar (void *);
extern double x;
void
foo (void)
{
char buf2 [32][1024];
bar (buf2 [(int) x]);
}
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