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riscv-gcc-1
Commit 22f89c92 by Jakub Jelinek Committed by Jakub Jelinek
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i386.md (set_got, [...]): Remove constraints from expanders. 

	* config/i386/i386.md (set_got, set_got_labelled, lwp_llwpcb,
	lwp_lwpval<mode>3, lwp_lwpins<mode>3): Remove constraints from
	expanders.
	* config/i386/sse.md (vec_interleave_high<mode>,
	vec_interleave_low<mode>, <avx512>_vpermi2var<mode>3_maskz,
	<avx512>_vpermt2var<mode>3_maskz): Likewise.

From-SVN: r236045
parent 8964ed82
Showing with 51 additions and 42 deletions
gcc/ChangeLog
2016-05-09 Jakub Jelinek <jakub@redhat.com>
* config/i386/i386.md (set_got, set_got_labelled, lwp_llwpcb,
lwp_lwpval<mode>3, lwp_lwpins<mode>3): Remove constraints from
expanders.
* config/i386/sse.md (vec_interleave_high<mode>,
vec_interleave_low<mode>, <avx512>_vpermi2var<mode>3_maskz,
<avx512>_vpermt2var<mode>3_maskz): Likewise.
2016-05-04 Aaron Sawdey <acsawdey@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_reassociation_width): Add
......
gcc/config/i386/i386.md
......@@ -12505,7 +12505,7 @@
(define_expand "set_got"
[(parallel
[(set (match_operand:SI 0 "register_operand" "=r")
[(set (match_operand:SI 0 "register_operand")
(unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
(clobber (reg:CC FLAGS_REG))])]
"!TARGET_64BIT"
......@@ -12525,7 +12525,7 @@
(define_expand "set_got_labelled"
[(parallel
[(set (match_operand:SI 0 "register_operand" "=r")
[(set (match_operand:SI 0 "register_operand")
(unspec:SI [(label_ref (match_operand 1))]
UNSPEC_SET_GOT))
(clobber (reg:CC FLAGS_REG))])]
......@@ -19024,7 +19024,7 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "lwp_llwpcb"
[(unspec_volatile [(match_operand 0 "register_operand" "r")]
[(unspec_volatile [(match_operand 0 "register_operand")]
UNSPECV_LLWP_INTRINSIC)]
"TARGET_LWP")
......@@ -19038,7 +19038,7 @@
(set_attr "length" "5")])
(define_expand "lwp_slwpcb"
[(set (match_operand 0 "register_operand" "=r")
[(set (match_operand 0 "register_operand")
(unspec_volatile [(const_int 0)] UNSPECV_SLWP_INTRINSIC))]
"TARGET_LWP"
{
......@@ -19062,9 +19062,9 @@
(set_attr "length" "5")])
(define_expand "lwp_lwpval<mode>3"
[(unspec_volatile [(match_operand:SWI48 1 "register_operand" "r")
(match_operand:SI 2 "nonimmediate_operand" "rm")
(match_operand:SI 3 "const_int_operand" "i")]
[(unspec_volatile [(match_operand:SWI48 1 "register_operand")
(match_operand:SI 2 "nonimmediate_operand")
(match_operand:SI 3 "const_int_operand")]
UNSPECV_LWPVAL_INTRINSIC)]
"TARGET_LWP"
;; Avoid unused variable warning.
......@@ -19084,11 +19084,11 @@
(define_expand "lwp_lwpins<mode>3"
[(set (reg:CCC FLAGS_REG)
(unspec_volatile:CCC [(match_operand:SWI48 1 "register_operand" "r")
(match_operand:SI 2 "nonimmediate_operand" "rm")
(match_operand:SI 3 "const_int_operand" "i")]
(unspec_volatile:CCC [(match_operand:SWI48 1 "register_operand")
(match_operand:SI 2 "nonimmediate_operand")
(match_operand:SI 3 "const_int_operand")]
UNSPECV_LWPINS_INTRINSIC))
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(set (match_operand:QI 0 "nonimmediate_operand")
(eq:QI (reg:CCC FLAGS_REG) (const_int 0)))]
"TARGET_LWP")
......
gcc/config/i386/sse.md
......@@ -11899,9 +11899,9 @@
(set_attr "mode" "TI")])
(define_expand "vec_interleave_high<mode>"
[(match_operand:VI_256 0 "register_operand" "=x")
(match_operand:VI_256 1 "register_operand" "x")
(match_operand:VI_256 2 "nonimmediate_operand" "xm")]
[(match_operand:VI_256 0 "register_operand")
(match_operand:VI_256 1 "register_operand")
(match_operand:VI_256 2 "nonimmediate_operand")]
"TARGET_AVX2"
{
rtx t1 = gen_reg_rtx (<MODE>mode);
......@@ -11917,9 +11917,9 @@
})
(define_expand "vec_interleave_low<mode>"
[(match_operand:VI_256 0 "register_operand" "=x")
(match_operand:VI_256 1 "register_operand" "x")
(match_operand:VI_256 2 "nonimmediate_operand" "xm")]
[(match_operand:VI_256 0 "register_operand")
(match_operand:VI_256 1 "register_operand")
(match_operand:VI_256 2 "nonimmediate_operand")]
"TARGET_AVX2"
{
rtx t1 = gen_reg_rtx (<MODE>mode);
......@@ -17244,11 +17244,11 @@
(set_attr "mode" "<sseinsnmode>")])
(define_expand "<avx512>_vpermi2var<mode>3_maskz"
[(match_operand:VI48F 0 "register_operand" "=v")
(match_operand:VI48F 1 "register_operand" "v")
(match_operand:<sseintvecmode> 2 "register_operand" "0")
(match_operand:VI48F 3 "nonimmediate_operand" "vm")
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")]
[(match_operand:VI48F 0 "register_operand")
(match_operand:VI48F 1 "register_operand")
(match_operand:<sseintvecmode> 2 "register_operand")
(match_operand:VI48F 3 "nonimmediate_operand")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
"TARGET_AVX512F"
{
emit_insn (gen_<avx512>_vpermi2var<mode>3_maskz_1 (
......@@ -17272,11 +17272,11 @@
})
(define_expand "<avx512>_vpermi2var<mode>3_maskz"
[(match_operand:VI2_AVX512VL 0 "register_operand" "=v")
(match_operand:VI2_AVX512VL 1 "register_operand" "v")
(match_operand:<sseintvecmode> 2 "register_operand" "0")
(match_operand:VI2_AVX512VL 3 "nonimmediate_operand" "vm")
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")]
[(match_operand:VI2_AVX512VL 0 "register_operand")
(match_operand:VI2_AVX512VL 1 "register_operand")
(match_operand:<sseintvecmode> 2 "register_operand")
(match_operand:VI2_AVX512VL 3 "nonimmediate_operand")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
"TARGET_AVX512BW"
{
emit_insn (gen_<avx512>_vpermi2var<mode>3_maskz_1 (
......@@ -17373,11 +17373,11 @@
(set_attr "mode" "<sseinsnmode>")])
(define_expand "<avx512>_vpermt2var<mode>3_maskz"
[(match_operand:VI48F 0 "register_operand" "=v")
(match_operand:<sseintvecmode> 1 "register_operand" "v")
(match_operand:VI48F 2 "register_operand" "0")
(match_operand:VI48F 3 "nonimmediate_operand" "vm")
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")]
[(match_operand:VI48F 0 "register_operand")
(match_operand:<sseintvecmode> 1 "register_operand")
(match_operand:VI48F 2 "register_operand")
(match_operand:VI48F 3 "nonimmediate_operand")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
"TARGET_AVX512F"
{
emit_insn (gen_<avx512>_vpermt2var<mode>3_maskz_1 (
......@@ -17387,11 +17387,11 @@
})
(define_expand "<avx512>_vpermt2var<mode>3_maskz"
[(match_operand:VI1_AVX512VL 0 "register_operand" "=v")
(match_operand:<sseintvecmode> 1 "register_operand" "v")
(match_operand:VI1_AVX512VL 2 "register_operand" "0")
(match_operand:VI1_AVX512VL 3 "nonimmediate_operand" "vm")
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")]
[(match_operand:VI1_AVX512VL 0 "register_operand")
(match_operand:<sseintvecmode> 1 "register_operand")
(match_operand:VI1_AVX512VL 2 "register_operand")
(match_operand:VI1_AVX512VL 3 "nonimmediate_operand")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
"TARGET_AVX512VBMI"
{
emit_insn (gen_<avx512>_vpermt2var<mode>3_maskz_1 (
......@@ -17401,11 +17401,11 @@
})
(define_expand "<avx512>_vpermt2var<mode>3_maskz"
[(match_operand:VI2_AVX512VL 0 "register_operand" "=v")
(match_operand:<sseintvecmode> 1 "register_operand" "v")
(match_operand:VI2_AVX512VL 2 "register_operand" "0")
(match_operand:VI2_AVX512VL 3 "nonimmediate_operand" "vm")
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")]
[(match_operand:VI2_AVX512VL 0 "register_operand")
(match_operand:<sseintvecmode> 1 "register_operand")
(match_operand:VI2_AVX512VL 2 "register_operand")
(match_operand:VI2_AVX512VL 3 "nonimmediate_operand")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
"TARGET_AVX512BW"
{
emit_insn (gen_<avx512>_vpermt2var<mode>3_maskz_1 (
......
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