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Commit 22ac2c2f by Andreas Krebbel Committed by Andreas Krebbel
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config.gcc: Enable zEC12 for with-arch and with-tune configure switches. 

2012-10-10  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* config.gcc: Enable zEC12 for with-arch and with-tune
          configure switches.
	* common/config/s390/s390-common.c (processor_flags_table): Add
	zEC12 entry.
	* config/s390/2827.md: New file.
	* config/s390/s390-opts.h (enum processor_type): Add
	PROCESSOR_2827_ZEC12.
	* config/s390/s390.h (enum processor_flags): Add PF_ZEC12.
	(TARGET_CPU_ZEC12, TARGET_ZEC12): New macro definitions.
	* config/s390/s390.c (zEC12_cost): New definition.
	(s390_option_override): Set costs for zEC12.
	Set parameter defaults for zEC12.
	(legitimate_reload_fp_constant_p): Adjust comment.
	(preferred_la_operand_p): Adjust comment.
	(s390_expand_insv): Generate insv pattern without CC clobber for
	zEC12.
	(s390_adjust_priority): Add zEC12 check.
	(s390_issue_rate): Return 2 for zEC12.
	(s390_reorg): Enable code optimizations for zEC12.
	(s390_sched_reorder): Reorder insns according to OOO attributes.
	(s390_get_sched_attrmask): New function.
	(s390_sched_score): New function.
	(s390_sched_variable_issue): Update s390_sched_state.
	(s390_sched_init): Reset s390_sched_state.
	(s390_loop_unroll_adjust): Enable for zEC12.
	* config/s390/s390.opt: Add zEC12 processor type value.
	* config/s390/s390.md: Enable mnemonic attribute.
	(attr cpu, cpu_facility): Add zEC12.
	Include 2827.md.
	("*insv<mode>_zEC12", "*insv<mode>_zEC12_noshift")
	("*load_and_trap<mode>"): New insn definition.
	("*cmp_and_trap_unsigned_int<mode>"): Add clt and clgt.

From-SVN: r192289
parent ce8aa074
Showing with 131 additions and 12 deletions
gcc/ChangeLog
2012-10-10 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* config.gcc: Enable zEC12 for with-arch and with-tune
configure switches.
* common/config/s390/s390-common.c (processor_flags_table): Add
zEC12 entry.
* config/s390/2827.md: New file.
* config/s390/s390-opts.h (enum processor_type): Add
PROCESSOR_2827_ZEC12.
* config/s390/s390.h (enum processor_flags): Add PF_ZEC12.
(TARGET_CPU_ZEC12, TARGET_ZEC12): New macro definitions.
* config/s390/s390.c (zEC12_cost): New definition.
(s390_option_override): Set costs for zEC12.
Set parameter defaults for zEC12.
(legitimate_reload_fp_constant_p): Adjust comment.
(preferred_la_operand_p): Adjust comment.
(s390_expand_insv): Generate insv pattern without CC clobber for
zEC12.
(s390_adjust_priority): Add zEC12 check.
(s390_issue_rate): Return 2 for zEC12.
(s390_reorg): Enable code optimizations for zEC12.
(s390_sched_reorder): Reorder insns according to OOO attributes.
(s390_get_sched_attrmask): New function.
(s390_sched_score): New function.
(s390_sched_variable_issue): Update s390_sched_state.
(s390_sched_init): Reset s390_sched_state.
(s390_loop_unroll_adjust): Enable for zEC12.
* config/s390/s390.opt: Add zEC12 processor type value.
* config/s390/s390.md: Enable mnemonic attribute.
(attr cpu, cpu_facility): Add zEC12.
Include 2827.md.
("*insv<mode>_zEC12", "*insv<mode>_zEC12_noshift")
("*load_and_trap<mode>"): New insn definition.
("*cmp_and_trap_unsigned_int<mode>"): Add clt and clgt.
2012-10-09 David S. Miller <davem@davemloft.net>
* config/sparc/sparc.md (type attribute): Add new types 'visl'
......
gcc/common/config/s390/s390-common.c
......@@ -41,7 +41,9 @@ EXPORTED_CONST int processor_flags_table[] =
/* z10 */ PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT
| PF_EXTIMM | PF_DFP | PF_Z10,
/* z196 */ PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT
| PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196
| PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196,
/* zEC12 */ PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT
| PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196 | PF_ZEC12
};
/* Change optimizations to be performed, depending on the
......
gcc/config.gcc
......@@ -3355,7 +3355,7 @@ case "${target}" in
for which in arch tune; do
eval "val=\$with_$which"
case ${val} in
"" | g5 | g6 | z900 | z990 | z9-109 | z9-ec | z10 | z196)
"" | g5 | g6 | z900 | z990 | z9-109 | z9-ec | z10 | z196 | zEC12)
# OK
;;
*)
......
gcc/config/s390/s390-opts.h
......@@ -35,6 +35,7 @@ enum processor_type
PROCESSOR_2094_Z9_EC,
PROCESSOR_2097_Z10,
PROCESSOR_2817_Z196,
PROCESSOR_2827_ZEC12,
PROCESSOR_max
};
......
gcc/config/s390/s390.h
......@@ -34,7 +34,8 @@ enum processor_flags
PF_EXTIMM = 8,
PF_DFP = 16,
PF_Z10 = 32,
PF_Z196 = 64
PF_Z196 = 64,
PF_ZEC12 = 128
};
/* This is necessary to avoid a warning about comparing different enum
......@@ -59,6 +60,8 @@ enum processor_flags
(s390_arch_flags & PF_Z10)
#define TARGET_CPU_Z196 \
(s390_arch_flags & PF_Z196)
#define TARGET_CPU_ZEC12 \
(s390_arch_flags & PF_ZEC12)
/* These flags indicate that the generated code should run on a cpu
providing the respective hardware facility when run in
......@@ -74,6 +77,8 @@ enum processor_flags
(TARGET_ZARCH && TARGET_CPU_Z10)
#define TARGET_Z196 \
(TARGET_ZARCH && TARGET_CPU_Z196)
#define TARGET_ZEC12 \
(TARGET_ZARCH && TARGET_CPU_ZEC12)
#define TARGET_AVOID_CMP_AND_BRANCH (s390_tune == PROCESSOR_2817_Z196)
......
gcc/config/s390/s390.md
......@@ -260,6 +260,8 @@
z196_cracked"
(const_string "none"))
(define_attr "mnemonic" "unknown" (const_string "unknown"))
;; Length in bytes.
(define_attr "length" ""
......@@ -273,10 +275,10 @@
;; distinguish between g5 and g6, but there are differences between the two
;; CPUs could in theory be modeled.
(define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196"
(define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12"
(const (symbol_ref "s390_tune_attr")))
(define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10,z196"
(define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10,z196,zEC12"
(const_string "standard"))
(define_attr "enabled" ""
......@@ -309,6 +311,10 @@
(and (eq_attr "cpu_facility" "z196")
(match_test "TARGET_Z196"))
(const_int 1)
(and (eq_attr "cpu_facility" "zEC12")
(match_test "TARGET_ZEC12"))
(const_int 1)]
(const_int 0)))
......@@ -325,6 +331,9 @@
;; Pipeline description for z196
(include "2817.md")
;; Pipeline description for zEC12
(include "2827.md")
;; Predicates
(include "predicates.md")
......@@ -3360,6 +3369,28 @@
FAIL;
})
(define_insn "*insv<mode>_zEC12"
[(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
(match_operand 1 "const_int_operand" "I")
(match_operand 2 "const_int_operand" "I"))
(match_operand:GPR 3 "nonimmediate_operand" "d"))]
"TARGET_ZEC12
&& (INTVAL (operands[1]) + INTVAL (operands[2])) <=
GET_MODE_BITSIZE (<MODE>mode)"
{
int start = INTVAL (operands[2]);
int size = INTVAL (operands[1]);
int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
operands[2] = GEN_INT (offset + start); /* start bit position */
operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
start - size); /* left shift count */
return "risbgn\t%0,%3,%b2,%b1,%b4";
}
[(set_attr "op_type" "RIE")])
(define_insn "*insv<mode>_z10"
[(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
(match_operand 1 "const_int_operand" "I")
......@@ -3386,6 +3417,34 @@
; and op1 with a mask being 1 for the selected bits and 0 for the rest
; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
(define_insn "*insv<mode>_zEC12_noshift"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
(ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
(match_operand 2 "const_int_operand" "n"))
(and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
(match_operand 4 "const_int_operand" "n"))))]
"TARGET_ZEC12
&& s390_contiguous_bitmask_p (INTVAL (operands[2]),
GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
&& INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
{
int start;
int size;
s390_contiguous_bitmask_p (INTVAL (operands[2]),
GET_MODE_BITSIZE (<MODE>mode), &start, &size);
operands[5] = GEN_INT (64 - start - size); /* start bit position */
operands[6] = GEN_INT (64 - 1 - start); /* end bit position */
operands[7] = const0_rtx; /* left shift count */
return "risbgn\t%0,%1,%b5,%b6,%b7";
}
[(set_attr "op_type" "RIE")])
; and op1 with a mask being 1 for the selected bits and 0 for the rest
; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
(define_insn "*insv<mode>_z10_noshift"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
(ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
......@@ -7894,19 +7953,33 @@
(set_attr "type" "branch")
(set_attr "z10prop" "z10_super_c,z10_super")])
; clrt, clgrt, clfit, clgit
; clrt, clgrt, clfit, clgit, clt, clgt
(define_insn "*cmp_and_trap_unsigned_int<mode>"
[(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
[(match_operand:GPR 1 "register_operand" "d,d")
(match_operand:GPR 2 "nonmemory_operand" "d,D")])
[(match_operand:GPR 1 "register_operand" "d,d, d")
(match_operand:GPR 2 "general_operand" "d,D,RT")])
(const_int 0))]
"TARGET_Z10"
"@
cl<g>rt%C0\t%1,%2
cl<gf>it%C0\t%1,%x2"
[(set_attr "op_type" "RRF,RIE")
(set_attr "type" "branch")
(set_attr "z10prop" "z10_super_c,z10_super")])
cl<gf>it%C0\t%1,%x2
cl<g>t%C0\t%1,%2"
[(set_attr "op_type" "RRF,RIE,RSY")
(set_attr "type" "branch")
(set_attr "z10prop" "z10_super_c,z10_super,*")
(set_attr "cpu_facility" "z10,z10,zEC12")])
; lat, lgat
(define_insn "*load_and_trap<mode>"
[(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
(const_int 0))
(const_int 0))
(set (match_operand:GPR 1 "register_operand" "=d")
(match_dup 0))]
"TARGET_ZEC12"
"l<g>at\t%1,%0"
[(set_attr "op_type" "RXY")])
;;
;;- Loop instructions.
......
gcc/config/s390/s390.opt
......@@ -73,6 +73,9 @@ Enum(processor_type) String(z10) Value(PROCESSOR_2097_Z10)
EnumValue
Enum(processor_type) String(z196) Value(PROCESSOR_2817_Z196)
EnumValue
Enum(processor_type) String(zEC12) Value(PROCESSOR_2827_ZEC12)
mbackchain
Target Report Mask(BACKCHAIN)
Maintain backchain pointer
......
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