Skip to content

R
riscv-gcc-1
Commit 223a9d64 by Naveen.H.S Committed by Nick Clifton
Options

configure.ac: Support all v850 targets. 

        * configure.ac: Support all v850 targets.
        * configure: Regenerate.

        * config/v850/lib1funcs.asm (save_r2_r31, return_r2_r31,
        save_r20_r31, return_r20_r31, save_r21_r31, return_r21_r31,
        save_r22_r31, return_r22_r31, save_r23_r31, return_r23_r31,
        save_r24_r31, return_r24_r31, save_r25_r31, return_r25_r31,
        save_r26_r31, return_r26_r31, save_r27_r31, return_r27_r31,
        save_r28_r31, return_r28_r31, save_r29_r31, return_r29_r31,
        save_r31, return_r31, save_interrupt, return_interrupt,
        save_all_interrupt, return_all_interrupt, L_save_r2_r31,
        L_return_interrupt, callt_return_interrupt, L_restore_all_interrupt,
        L_save_##START##_r31c, L_callt_save_r31c: Updated as per the
        new ABI requirements.
        save_r6_r9, L_callt_save_r6_r9: Remove.
        * config/v850/predicates.md (even_reg_operand, disp23_operand,
        const_float_1_operand const_float_0_operand): New Predicates.
        (pattern_is_ok_for_prepare, pattern_is_ok_for_prologue,
        pattern_is_ok_for_epilogue): Update as per the ABI requirements.
        * config/v850/t-v850: Update multilibs for new target variants.
        (save_varargs, callt_save_varargs, callt_save_r6_r9): Remove.
        * config/v850/t-v850e: Likewise.
        * config/v850/v850.c (v850_issue_rate): New.
        (v850_strict_argument_naming): New.
        (function_arg): Modify to generate a different ABI.
        (print_operand): Update case 'z' to support float modes.
        (output_move_single): Modify to generate appropriate and better
        assembly.
        (v850_float_z_comparison_operator, v850_select_cc_mode,
        v850_float_nz_comparison_operator,  v850_gen_float_compare,
        v850_gen_compare): New functions to support comparison of
        float values.
        (ep_memory_offset): Add support for V850E2 targets.
        (INTERRUPT_FIXED_NUM, INTERRUPT_ALL_SAVE_NUM): Update.
        (INTERRUPT_REGPARM_NUM): Remove.
        (compute_register_save_size): Add extra case to save/restore
        long call.
        (use_prolog_function): New function to support prologue.
        (expand_prologue): Add support for V850E2 targets and modified
        as per the current ABI requirements.
        (expand_epilogue): Likewise.
        (construct_restore_jr): Modify based on TARGET_LONG_CALLS.
        (construct_save_jarl): Likewise.
        (construct_dispose_instruction): Update as per the current ABI
        requirements.
        (construct_prepare_instruction): Likewise.
        * config/v850/v850.h(TARGET_CPU_DEFAULT): Add target predefines.
        (TARGET_CPU_v850e2, TARGET_CPU_v850e2v3): Define
        (CPP_SPEC): Updated to support v850e2 targets.
        (STRICT_ALIGNMENT): Modified.
        (FIRST_PSEUDO_REGISTER): Updated to add even registers.
        (FIXED_REGISTERS): Likewise.
        (CALL_USED_REGISTERS): Likewise.
        (CONDITIONAL_REGISTER_USAGE): Updated.
        (HARD_REGNO_MODE_OK): Updated.
        (reg_class): Updated to add even registers.
        (REG_CLASS_NAMES): Likewise.
        (REG_CLASS_CONTENTS): Likewise.
        (REGNO_REG_CLASS): Updated for CC registers.
        (REG_CLASS_FROM_LETTER): Added support for even registers.
        (REGNO_OK_FOR_BASE_P): Updated for CC registers.
        (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, LINK_POINTER_REGNUM,
        ARG_POINTER_REGNUM): Updated.
        (FUNCTION_ARG_ADVANCE): Define.
        (REG_PARM_STACK_SPACE): Update as per the current ABI requirements.
        (OUTGOING_REG_PARM_STACK_SPACE): Remove.
        (EXTRA_CONSTRAINT): Add new constraint 'W' for 23-bit displacement.
        (GO_IF_LEGITIMATE_ADDRESS): Updated.
        (SELECT_CC_MODE): Define.
        (REGISTER_NAMES): Updated to add psw and fcc registers.
        (ADDITIONAL_REGISTER_NAMES): Updated.
        (ASM_OUTPUT_ADDR_DIFF_ELT): Updated to support new targets.
        (JUMP_TABLES_IN_TEXT_SECTION): Updated.
        * config/v850/v850.md (define_constants): Define new constants.
        (type): Update store,bit1,macc,div,fpu and single attributes.
        (cpu): New attribute.
        (cc): Add set_z attribute.
        (unsign23byte_load, sign23byte_load, unsign23hword_load,
        sign23hword_load, 23word_load, 23byte_store, 23hword_store,
        23word_store): New instructions for 23-bit displacement load and
        store.
        (movqi_internal, movhi_internal): Update the attributes.
        (movsi, movsi_internal_v850e): Updated to support v850e2 targets.
        (movsi_internal_v850e, movsi_internal, movsf_internal): Update
        the attributes.
        (v850_tst1): Modified using CC_REGNUM.
        (tstsi): Remove.
        (cmpsi): Modified as define_expand from define_insn.
        (cmpsi_insn, cmpsf, cmpdf): New instructions.
        (addsi3, subsi3, negsi2, divmodsi4, udivmodsi4, divmodhi4,
        udivmodhi4, v850_clr1_1, v850_clr1_2, v850_clr1_3, andsi3,
        v850_set1_1, v850_set1_3, iorsi3, v850_not1_1, v850_not1_3, xorsi3,
        one_cmplsi2): Clobber the CC_REGNUM register.
        (v850_clr1_1, v850_clr1_2, v850_clr1_3, andsi3, v850_set1_1,
        v850_set1_2, v850_set1_3, iorsi3, v850_not1_1, v850_not1_2,
        v850_not1_3, xorsi3, one_cmplsi2): Update the attributes
        accordingly.
        (setf_insn, set_z_insn, set_nz_insn): New instructions for
        v850e2v3 target.
        (movsicc_normal_cc, movsicc_reversed_cc): New instructions.
        (movsicc, movsicc_normal, movsicc_reversed): Add support for V850E2
        targets.
        (sasf_1, sasf_2): Remove.
        (sasf): New instruction.
        (rotlhi3, rotlhi3_8, rotlsi3, rotlsi3_16): Update to support V850E2
        targets. CC_REGNUM register is clobbered and attributes are
        updated.
        (branch_z_normal, branch_z_invert, branch_nz_normal,
        branch_nz_invert): New branch related instructions.
        (jump): Updated the attributes.
        (switch): Update to support new targets. CC_REGNUM register is
        clobbered and attributes are updated.
        (call_internal_short, call_internal_long, call_value_internal_short,
        call_value_internal_long): Updated the attributes.
        (zero_extendhisi2, zero_extendqisi2): CC_REGNUM register is
        clobbered and attributes are updated.
        (extendhisi_insn, extendhisi2, extendqisi_insn, extendqisi2):
        Update to support new targets. CC_REGNUM register is clobbered.
        (ashlsi3_v850e2, lshrsi3_v850e2, ashrsi3_v850e2): New shift
        instructions.
        (lshrsi3, ashrsi3): CC_REGNUM register is clobbered and attributes
        are updated.
        (ffssi2, addsf3, adddf3, subsf3, subdf3, mulsf3, muldf3, divsf3,
        divdf3, minsf3, mindf3, maxsf3, maxdf3, abssf2, absdf2, negsf2,
        negdf2, sqrtsf2, sqrtdf2, truncsfsi2, truncdfsi2, floatsisf2,
        floatsidf2, extendsfdf2, extenddfsf2, recipsf2, recipdf2,
        rsqrtsf2, rsqrtdf2, maddsf4, msubsf4, nmaddsf4, nmsubsf4,
        cmpsf_le_insn, cmpsf_lt_insn, cmpsf_ge_insn, cmpsf_gt_insn,
        cmpsf_eq_insn, cmpsf_ne_insn, cmpdf_le_insn, cmpdf_lt_insn,
        cmpdf_ge_insn, cmpdf_gt_insn, cmpdf_eq_insn, cmpdf_ne_insn, trfsr,
        movsfcc, movdfcc, movsfcc_z_insn, movsfcc_nz_insn, movdfcc_z_insn,
        movdfcc_nz_insn, movedfcc_z_zero, movedfcc_nz_zero): New floating
        point instructions defined for V850e2v3 target.
        (callt_save_interrupt, callt_return_interrupt, return_interrupt):
        Add support for V850E2 targets and CC_REGNUM register is clobbered.
        (callt_save_all_interrupt, callt_restore_all_interrupt): Add
        support for new targets.
        * config/v850/v850-modes.def: New file.
        * config/v850/v850.opt(mstrict-align): Remove.
        (mno-strict-align, mjump-tables-in-data-section, mv850e2,
        mv850e2v3): New command line options for V850.
        * config.gcc: Update the newly added files.
        * doc/invoke.texi: Update the newly added command line options for
        V850 target.

From-SVN: r162530
parent 4e89a3fa
Showing with 297 additions and 41 deletions
ChangeLog
2010-07-26 Naveen.H.S <naveen.S@kpitcummins.com>
* configure.ac: Support all v850 targets.
* configure: Regenerate.
2010-07-23 Marc Glisse <marc.glisse@normalesup.org>
PR bootstrap/44455
......
configure
......@@ -3730,13 +3730,7 @@ case "${target}" in
v810-*-*)
noconfigdirs="$noconfigdirs bfd binutils gas gcc gdb ld target-libstdc++-v3 opcodes target-libgloss ${libgcj}"
;;
v850-*-*)
noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
;;
v850e-*-*)
noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
;;
v850ea-*-*)
v850*-*-*)
noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
;;
vax-*-vms)
......
configure.ac
......@@ -967,13 +967,7 @@ case "${target}" in
v810-*-*)
noconfigdirs="$noconfigdirs bfd binutils gas gcc gdb ld target-libstdc++-v3 opcodes target-libgloss ${libgcj}"
;;
v850-*-*)
noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
;;
v850e-*-*)
noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
;;
v850ea-*-*)
v850*-*-*)
noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
;;
vax-*-vms)
......
gcc/ChangeLog
2010-07-26 Naveen.H.S <naveen.S@kpitcummins.com>
* config/v850/lib1funcs.asm (save_r2_r31, return_r2_r31,
save_r20_r31, return_r20_r31, save_r21_r31, return_r21_r31,
save_r22_r31, return_r22_r31, save_r23_r31, return_r23_r31,
save_r24_r31, return_r24_r31, save_r25_r31, return_r25_r31,
save_r26_r31, return_r26_r31, save_r27_r31, return_r27_r31,
save_r28_r31, return_r28_r31, save_r29_r31, return_r29_r31,
save_r31, return_r31, save_interrupt, return_interrupt,
save_all_interrupt, return_all_interrupt, L_save_r2_r31,
L_return_interrupt, callt_return_interrupt, L_restore_all_interrupt,
L_save_##START##_r31c, L_callt_save_r31c: Updated as per the
new ABI requirements.
save_r6_r9, L_callt_save_r6_r9: Remove.
* config/v850/predicates.md (even_reg_operand, disp23_operand,
const_float_1_operand const_float_0_operand): New Predicates.
(pattern_is_ok_for_prepare, pattern_is_ok_for_prologue,
pattern_is_ok_for_epilogue): Update as per the ABI requirements.
* config/v850/t-v850: Update multilibs for new target variants.
(save_varargs, callt_save_varargs, callt_save_r6_r9): Remove.
* config/v850/t-v850e: Likewise.
* config/v850/v850.c (v850_issue_rate): New.
(v850_strict_argument_naming): New.
(function_arg): Modify to generate a different ABI.
(print_operand): Update case 'z' to support float modes.
(output_move_single): Modify to generate appropriate and better
assembly.
(v850_float_z_comparison_operator, v850_select_cc_mode,
v850_float_nz_comparison_operator, v850_gen_float_compare,
v850_gen_compare): New functions to support comparison of
float values.
(ep_memory_offset): Add support for V850E2 targets.
(INTERRUPT_FIXED_NUM, INTERRUPT_ALL_SAVE_NUM): Update.
(INTERRUPT_REGPARM_NUM): Remove.
(compute_register_save_size): Add extra case to save/restore
long call.
(use_prolog_function): New function to support prologue.
(expand_prologue): Add support for V850E2 targets and modified
as per the current ABI requirements.
(expand_epilogue): Likewise.
(construct_restore_jr): Modify based on TARGET_LONG_CALLS.
(construct_save_jarl): Likewise.
(construct_dispose_instruction): Update as per the current ABI
requirements.
(construct_prepare_instruction): Likewise.
* config/v850/v850.h(TARGET_CPU_DEFAULT): Add target predefines.
(TARGET_CPU_v850e2, TARGET_CPU_v850e2v3): Define
(CPP_SPEC): Updated to support v850e2 targets.
(STRICT_ALIGNMENT): Modified.
(FIRST_PSEUDO_REGISTER): Updated to add even registers.
(FIXED_REGISTERS): Likewise.
(CALL_USED_REGISTERS): Likewise.
(CONDITIONAL_REGISTER_USAGE): Updated.
(HARD_REGNO_MODE_OK): Updated.
(reg_class): Updated to add even registers.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(REGNO_REG_CLASS): Updated for CC registers.
(REG_CLASS_FROM_LETTER): Added support for even registers.
(REGNO_OK_FOR_BASE_P): Updated for CC registers.
(STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, LINK_POINTER_REGNUM,
ARG_POINTER_REGNUM): Updated.
(FUNCTION_ARG_ADVANCE): Define.
(REG_PARM_STACK_SPACE): Update as per the current ABI requirements.
(OUTGOING_REG_PARM_STACK_SPACE): Remove.
(EXTRA_CONSTRAINT): Add new constraint 'W' for 23-bit displacement.
(GO_IF_LEGITIMATE_ADDRESS): Updated.
(SELECT_CC_MODE): Define.
(REGISTER_NAMES): Updated to add psw and fcc registers.
(ADDITIONAL_REGISTER_NAMES): Updated.
(ASM_OUTPUT_ADDR_DIFF_ELT): Updated to support new targets.
(JUMP_TABLES_IN_TEXT_SECTION): Updated.
* config/v850/v850.md (define_constants): Define new constants.
(type): Update store,bit1,macc,div,fpu and single attributes.
(cpu): New attribute.
(cc): Add set_z attribute.
(unsign23byte_load, sign23byte_load, unsign23hword_load,
sign23hword_load, 23word_load, 23byte_store, 23hword_store,
23word_store): New instructions for 23-bit displacement load and
store.
(movqi_internal, movhi_internal): Update the attributes.
(movsi, movsi_internal_v850e): Updated to support v850e2 targets.
(movsi_internal_v850e, movsi_internal, movsf_internal): Update
the attributes.
(v850_tst1): Modified using CC_REGNUM.
(tstsi): Remove.
(cmpsi): Modified as define_expand from define_insn.
(cmpsi_insn, cmpsf, cmpdf): New instructions.
(addsi3, subsi3, negsi2, divmodsi4, udivmodsi4, divmodhi4,
udivmodhi4, v850_clr1_1, v850_clr1_2, v850_clr1_3, andsi3,
v850_set1_1, v850_set1_3, iorsi3, v850_not1_1, v850_not1_3, xorsi3,
one_cmplsi2): Clobber the CC_REGNUM register.
(v850_clr1_1, v850_clr1_2, v850_clr1_3, andsi3, v850_set1_1,
v850_set1_2, v850_set1_3, iorsi3, v850_not1_1, v850_not1_2,
v850_not1_3, xorsi3, one_cmplsi2): Update the attributes
accordingly.
(setf_insn, set_z_insn, set_nz_insn): New instructions for
v850e2v3 target.
(movsicc_normal_cc, movsicc_reversed_cc): New instructions.
(movsicc, movsicc_normal, movsicc_reversed): Add support for V850E2
targets.
(sasf_1, sasf_2): Remove.
(sasf): New instruction.
(rotlhi3, rotlhi3_8, rotlsi3, rotlsi3_16): Update to support V850E2
targets. CC_REGNUM register is clobbered and attributes are
updated.
(branch_z_normal, branch_z_invert, branch_nz_normal,
branch_nz_invert): New branch related instructions.
(jump): Updated the attributes.
(switch): Update to support new targets. CC_REGNUM register is
clobbered and attributes are updated.
(call_internal_short, call_internal_long, call_value_internal_short,
call_value_internal_long): Updated the attributes.
(zero_extendhisi2, zero_extendqisi2): CC_REGNUM register is
clobbered and attributes are updated.
(extendhisi_insn, extendhisi2, extendqisi_insn, extendqisi2):
Update to support new targets. CC_REGNUM register is clobbered.
(ashlsi3_v850e2, lshrsi3_v850e2, ashrsi3_v850e2): New shift
instructions.
(lshrsi3, ashrsi3): CC_REGNUM register is clobbered and attributes
are updated.
(ffssi2, addsf3, adddf3, subsf3, subdf3, mulsf3, muldf3, divsf3,
divdf3, minsf3, mindf3, maxsf3, maxdf3, abssf2, absdf2, negsf2,
negdf2, sqrtsf2, sqrtdf2, truncsfsi2, truncdfsi2, floatsisf2,
floatsidf2, extendsfdf2, extenddfsf2, recipsf2, recipdf2,
rsqrtsf2, rsqrtdf2, maddsf4, msubsf4, nmaddsf4, nmsubsf4,
cmpsf_le_insn, cmpsf_lt_insn, cmpsf_ge_insn, cmpsf_gt_insn,
cmpsf_eq_insn, cmpsf_ne_insn, cmpdf_le_insn, cmpdf_lt_insn,
cmpdf_ge_insn, cmpdf_gt_insn, cmpdf_eq_insn, cmpdf_ne_insn, trfsr,
movsfcc, movdfcc, movsfcc_z_insn, movsfcc_nz_insn, movdfcc_z_insn,
movdfcc_nz_insn, movedfcc_z_zero, movedfcc_nz_zero): New floating
point instructions defined for V850e2v3 target.
(callt_save_interrupt, callt_return_interrupt, return_interrupt):
Add support for V850E2 targets and CC_REGNUM register is clobbered.
(callt_save_all_interrupt, callt_restore_all_interrupt): Add
support for new targets.
* config/v850/v850-modes.def: New file.
* config/v850/v850.opt(mstrict-align): Remove.
(mno-strict-align, mjump-tables-in-data-section, mv850e2,
mv850e2v3): New command line options for V850.
* config.gcc: Update the newly added files.
* doc/invoke.texi: Update the newly added command line options for
V850 target.
2010-07-26 Richard Guenther <rguenther@suse.de>
PR tree-optimization/45052
......
gcc/config.gcc
......@@ -2517,6 +2517,7 @@ v850e1-*-*)
tm_p_file=v850/v850-protos.h
tmake_file=v850/t-v850e
md_file=v850/v850.md
extra_modes=v850/v850-modes.def
out_file=v850/v850.c
extra_options="${extra_options} v850/v850.opt"
if test x$stabs = xyes
......@@ -2534,6 +2535,7 @@ v850e-*-*)
tm_p_file=v850/v850-protos.h
tmake_file=v850/t-v850e
md_file=v850/v850.md
extra_modes=v850/v850-modes.def
out_file=v850/v850.c
extra_options="${extra_options} v850/v850.opt"
if test x$stabs = xyes
......
gcc/config/v850/predicates.md
......@@ -68,6 +68,17 @@
return register_operand (op, mode);
})
;; Return true if OP is a even number register.
(define_predicate "even_reg_operand"
(match_code "reg")
{
return (GET_CODE (op) == REG
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| ((REGNO (op) > 0) && (REGNO (op) < 32)
&& ((REGNO (op) & 1)==0))));
})
;; Return true if OP is a valid call operand.
(define_predicate "call_address_operand"
......@@ -79,7 +90,7 @@
return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
})
;; TODO: Add a comment here.
;; Return true if OP is a valid source operand for SImode move.
(define_predicate "movsi_source_operand"
(match_code "label_ref,symbol_ref,const_int,const_double,const,high,mem,reg,subreg")
......@@ -97,7 +108,21 @@
return general_operand (op, mode);
})
;; TODO: Add a comment here.
;; Return true if OP is a valid operand for 23 bit displacement
;; operations.
(define_predicate "disp23_operand"
(match_code "const_int")
{
if (GET_CODE (op) == CONST_INT
&& ((unsigned)(INTVAL (op)) >= 0x8000)
&& ((unsigned)(INTVAL (op)) < 0x400000))
return 1;
else
return 0;
})
;; Return true if OP is a symbol ref with 16-bit signed value.
(define_predicate "special_symbolref_operand"
(match_code "symbol_ref")
......@@ -115,7 +140,8 @@
return FALSE;
})
;; TODO: Add a comment here.
;; Return true if OP is a valid operand for bit related operations
;; containing only single 1 in its binary representation.
(define_predicate "power_of_two_operand"
(match_code "const_int")
......@@ -140,7 +166,7 @@
/* If there are no registers to save then the function prologue
is not suitable. */
if (count <= 2)
if (count <= (TARGET_LONG_CALLS ? 3 : 2))
return 0;
/* The pattern matching has already established that we are adjusting the
......@@ -198,18 +224,24 @@
}
/* Make sure that the last entries in the vector are clobbers. */
for (; i < count; i++)
vector_element = XVECEXP (op, 0, i++);
if (GET_CODE (vector_element) != CLOBBER
|| GET_CODE (XEXP (vector_element, 0)) != REG
|| REGNO (XEXP (vector_element, 0)) != 10)
return 0;
if (TARGET_LONG_CALLS)
{
vector_element = XVECEXP (op, 0, i);
vector_element = XVECEXP (op, 0, i++);
if (GET_CODE (vector_element) != CLOBBER
|| GET_CODE (XEXP (vector_element, 0)) != REG
|| !(REGNO (XEXP (vector_element, 0)) == 10
|| (TARGET_LONG_CALLS ? (REGNO (XEXP (vector_element, 0)) == 11) : 0 )))
|| REGNO (XEXP (vector_element, 0)) != 11)
return 0;
}
return 1;
return i == count;
})
;; Return nonzero if the given RTX is suitable for collapsing into
......@@ -239,7 +271,7 @@
(mem:SI (plus:SI (reg:SI 3) (match_operand:SI n "immediate_operand" "i"))))
*/
for (i = 3; i < count; i++)
for (i = 2; i < count; i++)
{
rtx vector_element = XVECEXP (op, 0, i);
rtx dest;
......@@ -372,13 +404,16 @@
*/
for (i = 2; i < count; i++)
for (i = 1; i < count; i++)
{
rtx vector_element = XVECEXP (op, 0, i);
rtx dest;
rtx src;
rtx plus;
if (GET_CODE (vector_element) == CLOBBER)
continue;
if (GET_CODE (vector_element) != SET)
return 0;
......@@ -406,14 +441,15 @@
space just acquired by the first operand then abandon this quest.
Note: the test is <= because both values are negative. */
if (INTVAL (XEXP (plus, 1))
<= INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)))
< INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)))
return 0;
}
return 1;
})
;; TODO: Add a comment here.
;; Return true if OP is a valid operand for bit related operations
;; containing only single 0 in its binary representation.
(define_predicate "not_power_of_two_operand"
(match_code "const_int")
......@@ -436,3 +472,31 @@
return 0;
return 1;
})
;; Return true if OP is a float value operand with value as 1.
(define_predicate "const_float_1_operand"
(match_code "const_int")
{
if (GET_CODE (op) != CONST_DOUBLE
|| mode != GET_MODE (op)
|| (mode != DFmode && mode != SFmode))
return 0;
return op == CONST1_RTX(mode);
})
;; Return true if OP is a float value operand with value as 0.
(define_predicate "const_float_0_operand"
(match_code "const_int")
{
if (GET_CODE (op) != CONST_DOUBLE
|| mode != GET_MODE (op)
|| (mode != DFmode && mode != SFmode))
return 0;
return op == CONST0_RTX(mode);
})
gcc/config/v850/t-v850
......@@ -46,7 +46,6 @@ LIB1ASMFUNCS = _mulsi3 \
_save_28c \
_save_29c \
_save_31c \
_save_varargs \
_save_interrupt \
_save_all_interrupt \
_callt_save_20 \
......@@ -70,12 +69,10 @@ LIB1ASMFUNCS = _mulsi3 \
_callt_save_28c \
_callt_save_29c \
_callt_save_31c \
_callt_save_varargs \
_callt_save_interrupt \
_callt_save_all_interrupt \
_callt_save_r2_r29 \
_callt_save_r2_r31 \
_callt_save_r6_r9 \
_negdi2 \
_cmpdi2 \
_ucmpdi2 \
......@@ -100,10 +97,10 @@ fp-bit.c: $(srcdir)/config/fp-bit.c
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
# Create target-specific versions of the libraries
MULTILIB_OPTIONS = mv850e
MULTILIB_DIRNAMES = v850e
MULTILIB_OPTIONS = mv850/mv850e/mv850e2/mv850e2v3
MULTILIB_DIRNAMES = v850 v850e v850e2 v850e2v3
INSTALL_LIBGCC = install-multilib
MULTILIB_MATCHES = mv850e=mv850e1
MULTILIB_MATCHES = mv850e=mv850e1
TCFLAGS = -mno-app-regs -msmall-sld -Wa,-mwarn-signed-overflow -Wa,-mwarn-unsigned-overflow
......
gcc/config/v850/t-v850e
......@@ -45,7 +45,6 @@ LIB1ASMFUNCS = _mulsi3 \
_save_28c \
_save_29c \
_save_31c \
_save_varargs \
_save_interrupt \
_save_all_interrupt \
_callt_save_20 \
......@@ -69,12 +68,10 @@ LIB1ASMFUNCS = _mulsi3 \
_callt_save_28c \
_callt_save_29c \
_callt_save_31c \
_callt_save_varargs \
_callt_save_interrupt \
_callt_save_all_interrupt \
_callt_save_r2_r29 \
_callt_save_r2_r31 \
_callt_save_r6_r9 \
_negdi2 \
_cmpdi2 \
_ucmpdi2 \
......
gcc/config/v850/v850-modes.def 0 → 100644
/* Definitions of target machine for GNU compiler. NEC V850 series
Copyright (C) 2005
Free Software Foundation, Inc.
Contributed by NEC EL
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
CC_MODE (CC_FPU_LT);
CC_MODE (CC_FPU_LE);
CC_MODE (CC_FPU_GT);
CC_MODE (CC_FPU_GE);
CC_MODE (CC_FPU_EQ);
CC_MODE (CC_FPU_NE);
gcc/config/v850/v850-protos.h
......@@ -43,6 +43,11 @@ extern char * construct_restore_jr (rtx);
extern char * construct_dispose_instruction (rtx);
extern char * construct_prepare_instruction (rtx);
extern int ep_memory_operand (rtx, Mmode, int);
extern int v850_float_z_comparison_operator (rtx, Mmode);
extern int v850_float_nz_comparison_operator (rtx, Mmode);
extern rtx v850_gen_compare (enum rtx_code, Mmode, rtx, rtx);
extern Mmode v850_gen_float_compare (enum rtx_code, Mmode, rtx, rtx);
extern Mmode v850_select_cc_mode (RTX_CODE, rtx, rtx);
#ifdef TREE_CODE
extern rtx function_arg (CUMULATIVE_ARGS *, Mmode, tree, int);
#endif
......
gcc/config/v850/v850.opt
......@@ -66,10 +66,14 @@ mtda
Target RejectNegative Joined
Set the max size of data eligible for the TDA area
mstrict-align
Target Report Mask(STRICT_ALIGN)
mno-strict-align
Target Report Mask(NO_STRICT_ALIGN)
Enforce strict alignment
mjump-tables-in-data-section
Target Report Mask(JUMP_TABLES_IN_DATA_SECTION)
Enforce table jump
mUS-bit-set
Target Report Mask(US_BIT_SET)
......@@ -82,9 +86,17 @@ Target Report RejectNegative Mask(V850E)
Compile for the v850e processor
mv850e1
Target RejectNegative Mask(V850E) MaskExists
Target RejectNegative Mask(V850E1)
Compile for the v850e1 processor
mv850e2
Target Report RejectNegative Mask(V850E2)
Compile for the v850e2 processor
mv850e2v3
Target Report RejectNegative Mask(V850E2V3)
Compile for the v850e2v3 processor
mzda
Target RejectNegative Joined
Set the max size of data eligible for the ZDA area
gcc/doc/invoke.texi
......@@ -868,6 +868,8 @@ See RS/6000 and PowerPC Options.
-mtda=@var{n} -msda=@var{n} -mzda=@var{n} @gol
-mapp-regs -mno-app-regs @gol
-mdisable-callt -mno-disable-callt @gol
-mv850e2v3 @gol
-mv850e2 @gol
-mv850e1 @gol
-mv850e @gol
-mv850 -mbig-switch}
......@@ -16957,11 +16959,21 @@ the compiler. This setting is the default.
@opindex mno-app-regs
This option will cause r2 and r5 to be treated as fixed registers.
@item -mv850e2v3
@opindex mv850e2v3
Specify that the target processor is the V850E2V3. The preprocessor
constants @samp{__v850e2v3__} will be defined if
this option is used.
@item -mv850e2
@opindex mv850e2
Specify that the target processor is the V850E2. The preprocessor
constants @samp{__v850e2__} will be defined if
@item -mv850e1
@opindex mv850e1
Specify that the target processor is the V850E1. The preprocessor
constants @samp{__v850e1__} and @samp{__v850e__} will be defined if
this option is used.
@item -mv850e
@opindex mv850e
......@@ -16969,6 +16981,7 @@ Specify that the target processor is the V850E@. The preprocessor
constant @samp{__v850e__} will be defined if this option is used.
If neither @option{-mv850} nor @option{-mv850e} nor @option{-mv850e1}
nor @option{-mv850e2} nor @option{-mv850e2v3}
are defined then a default target processor will be chosen and the
relevant @samp{__v850*__} preprocessor constant will be defined.
......@@ -16978,7 +16991,7 @@ defined, regardless of which processor variant is the target.
@item -mdisable-callt
@opindex mdisable-callt
This option will suppress generation of the CALLT instruction for the
v850e and v850e1 flavors of the v850 architecture. The default is
v850e, v850e1, v850e2 and v850e2v3 flavors of the v850 architecture. The default is
@option{-mno-disable-callt} which allows the CALLT instruction to be used.
@end table
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment