var_shift_mask_1.c: Fix for ILP32

2017-07-10  Michael Collison <michael.collison@arm.com>

	* gcc.target/aarch64/var_shift_mask_1.c: Fix for ILP32

From-SVN: r250112

gcc/testsuite/ChangeLog

+2017-07-10  Michael Collison <michael.collison@arm.com>
+
+	* gcc.target/aarch64/var_shift_mask_1.c: Fix for ILP32
+
 2017-07-10  Uros Bizjak  <ubizjak@gmail.com>
 
 	PR target/81375

gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c

@@ -11,17 +11,17 @@ f1 (unsigned x, int y)
   return x << (y & 31);
 }
 
-unsigned long
-f2 (unsigned long x, int y)
+unsigned long long
+f2 (unsigned long long x, int y)
 {
   return x << (y & 63);
 }
 
-unsigned long
-f3 (unsigned long bit_addr, int y)
+unsigned long long
+f3 (unsigned long long bit_addr, int y)
 {
   unsigned long bitnumb = bit_addr & 63;
-  return (1L << bitnumb);
+  return (1LL << bitnumb);
 }
 
 unsigned int
@@ -31,28 +31,32 @@ f4 (unsigned int x, unsigned int y)
   return x >> y | (x << (32 - y));
 }
 
-unsigned long
-f5 (unsigned long x, unsigned long y)
+unsigned long long
+f5 (unsigned long long x, unsigned long long y)
 {
   y &= 63;
   return x >> y | (x << (64 - y));
 }
 
-unsigned long
-f6 (unsigned long x, unsigned long y)
+unsigned int
+f6 (unsigned int x, unsigned int y)
 {
+  return (x << (32 - (y & 31)));
+}
 
+unsigned long long
+f7 (unsigned long long x, unsigned long long y)
+{
   return (x << (64 - (y & 63)));
-
 }
 
-unsigned long
-f7 (unsigned long x, unsigned long y)
+unsigned long long
+f8 (unsigned long long x, unsigned long long y)
 {
   return (x << -(y & 63));
 }
 
-/* { dg-final { scan-assembler-times "lsl\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "lsl\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
 /* { dg-final { scan-assembler-times "lsl\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 4 } } */
 /* { dg-final { scan-assembler-times "ror\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 1 } } */
 /* { dg-final { scan-assembler-times "ror\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 1 } } */