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riscv-gcc-1
Commit 21375863 by Jeffrey A Law Committed by Jeff Law
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* mn10200.md (bset, bclr): Operand 0 is a read/write operand. 

From-SVN: r25134
parent 05a59650
Showing with 8 additions and 6 deletions
gcc/ChangeLog
...@@ -17,6 +17,8 @@ Wed Feb 10 09:57:08 1999 Mark Mitchell <mark@markmitchell.com> ...@@ -17,6 +17,8 @@ Wed Feb 10 09:57:08 1999 Mark Mitchell <mark@markmitchell.com>
Wed Feb 10 10:09:41 1999 Jeffrey A Law (law@cygnus.com) Wed Feb 10 10:09:41 1999 Jeffrey A Law (law@cygnus.com)
* mn10200.md (bset, bclr): Operand 0 is a read/write operand.
* reload1.c (reload_combine_note_store): Second argument is no * reload1.c (reload_combine_note_store): Second argument is no
longer unused/ignored. Handle multi-register hard regs. longer unused/ignored. Handle multi-register hard regs.
(move2add_note_store): Simplify. (move2add_note_store): Simplify.
......
gcc/config/mn10200/mn10200.md
...@@ -656,7 +656,7 @@ ...@@ -656,7 +656,7 @@
;; These clears a constant set of bits in memory or in a register. ;; These clears a constant set of bits in memory or in a register.
;; We must support register destinations to make reload happy. ;; We must support register destinations to make reload happy.
(define_insn "" (define_insn ""
[(set (match_operand:QI 0 "general_operand" "R,d") [(set (match_operand:QI 0 "general_operand" "+R,d")
(subreg:QI (subreg:QI
(and:HI (subreg:HI (match_dup 0) 0) (and:HI (subreg:HI (match_dup 0) 0)
(match_operand 1 "const_int_operand" "")) 0)) (match_operand 1 "const_int_operand" "")) 0))
...@@ -669,7 +669,7 @@ ...@@ -669,7 +669,7 @@
;; This clears a variable set of bits in memory or in a register. ;; This clears a variable set of bits in memory or in a register.
(define_insn "" (define_insn ""
[(set (match_operand:QI 0 "general_operand" "R,d") [(set (match_operand:QI 0 "general_operand" "+R,d")
(subreg:QI (subreg:QI
(and:HI (subreg:HI (match_dup 0) 0) (and:HI (subreg:HI (match_dup 0) 0)
(not:HI (match_operand:HI 1 "general_operand" "d,d"))) 0)) (not:HI (match_operand:HI 1 "general_operand" "d,d"))) 0))
...@@ -681,7 +681,7 @@ ...@@ -681,7 +681,7 @@
[(set_attr "cc" "clobber")]) [(set_attr "cc" "clobber")])
(define_insn "" (define_insn ""
[(set (match_operand:QI 0 "general_operand" "R,d") [(set (match_operand:QI 0 "general_operand" "+R,d")
(subreg:QI (subreg:QI
(and:HI (not:HI (match_operand:HI 1 "general_operand" "d,d")) (and:HI (not:HI (match_operand:HI 1 "general_operand" "d,d"))
(subreg:HI (match_dup 0) 0)) 0)) (subreg:HI (match_dup 0) 0)) 0))
...@@ -694,7 +694,7 @@ ...@@ -694,7 +694,7 @@
;; These set bits in memory. ;; These set bits in memory.
(define_insn "" (define_insn ""
[(set (match_operand:QI 0 "general_operand" "R,d") [(set (match_operand:QI 0 "general_operand" "+R,d")
(subreg:QI (subreg:QI
(ior:HI (subreg:HI (match_dup 0) 0) (ior:HI (subreg:HI (match_dup 0) 0)
(match_operand:HI 1 "general_operand" "d,d")) 0))] (match_operand:HI 1 "general_operand" "d,d")) 0))]
...@@ -705,11 +705,11 @@ ...@@ -705,11 +705,11 @@
[(set_attr "cc" "clobber")]) [(set_attr "cc" "clobber")])
(define_insn "" (define_insn ""
[(set (match_operand:QI 0 "general_operand" "R,d") [(set (match_operand:QI 0 "general_operand" "+R,d")
(subreg:QI (subreg:QI
(ior:HI (match_operand:HI 1 "general_operand" "d,d") (ior:HI (match_operand:HI 1 "general_operand" "d,d")
(subreg:HI (match_dup 0) 0)) 0))] (subreg:HI (match_dup 0) 0)) 0))]
"" "0"
"@ "@
bset %1,%0 bset %1,%0
or %1,%0" or %1,%0"
......
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