Commit 20fceb31 by Richard Sandiford Committed by Richard Sandiford

gcc/

	* defaults.h (HAVE_load_multiple, gen_load_multiple)
	(HAVE_store_multiple, gen_store_multiple): Delete.
	* target-insns.def (load_multiple, store_multiple): New targetm
	instruction patterns.
	* expr.c (move_block_to_reg, move_block_from_reg): Use them instead
	of HAVE_*/gen_* interface.

From-SVN: r225210
parent ccf5bbdd
2015-06-30 Richard Sandiford <richard.sandiford@arm.com>
* defaults.h (HAVE_load_multiple, gen_load_multiple)
(HAVE_store_multiple, gen_store_multiple): Delete.
* target-insns.def (load_multiple, store_multiple): New targetm
instruction patterns.
* expr.c (move_block_to_reg, move_block_from_reg): Use them instead
of HAVE_*/gen_* interface.
2015-06-30 Richard Sandiford <richard.sandiford@arm.com>
* defaults.h (HAVE_mem_thread_fence, gen_mem_thread_fence)
(HAVE_memory_barrier, gen_memory_barrier, HAVE_mem_signal_fence)
(gen_mem_signal_fence): Delete.
......
......@@ -1426,26 +1426,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define TARGET_VTABLE_USES_DESCRIPTORS 0
#endif
#ifndef HAVE_load_multiple
#define HAVE_load_multiple 0
static inline rtx
gen_load_multiple (rtx, rtx, rtx)
{
gcc_unreachable ();
return NULL;
}
#endif
#ifndef HAVE_store_multiple
#define HAVE_store_multiple 0
static inline rtx
gen_store_multiple (rtx, rtx, rtx)
{
gcc_unreachable ();
return NULL;
}
#endif
#ifndef HAVE_tablejump
#define HAVE_tablejump 0
static inline rtx
......
......@@ -1491,10 +1491,6 @@ emit_block_move_via_loop (rtx x, rtx y, rtx size,
void
move_block_to_reg (int regno, rtx x, int nregs, machine_mode mode)
{
int i;
rtx pat;
rtx_insn *last;
if (nregs == 0)
return;
......@@ -1502,12 +1498,12 @@ move_block_to_reg (int regno, rtx x, int nregs, machine_mode mode)
x = validize_mem (force_const_mem (mode, x));
/* See if the machine can do this with a load multiple insn. */
if (HAVE_load_multiple)
if (targetm.have_load_multiple ())
{
last = get_last_insn ();
pat = gen_load_multiple (gen_rtx_REG (word_mode, regno), x,
GEN_INT (nregs));
if (pat)
rtx_insn *last = get_last_insn ();
rtx first = gen_rtx_REG (word_mode, regno);
if (rtx_insn *pat = targetm.gen_load_multiple (first, x,
GEN_INT (nregs)))
{
emit_insn (pat);
return;
......@@ -1516,7 +1512,7 @@ move_block_to_reg (int regno, rtx x, int nregs, machine_mode mode)
delete_insns_since (last);
}
for (i = 0; i < nregs; i++)
for (int i = 0; i < nregs; i++)
emit_move_insn (gen_rtx_REG (word_mode, regno + i),
operand_subword_force (x, i, mode));
}
......@@ -1527,18 +1523,16 @@ move_block_to_reg (int regno, rtx x, int nregs, machine_mode mode)
void
move_block_from_reg (int regno, rtx x, int nregs)
{
int i;
if (nregs == 0)
return;
/* See if the machine can do this with a store multiple insn. */
if (HAVE_store_multiple)
if (targetm.have_store_multiple ())
{
rtx_insn *last = get_last_insn ();
rtx pat = gen_store_multiple (x, gen_rtx_REG (word_mode, regno),
GEN_INT (nregs));
if (pat)
rtx first = gen_rtx_REG (word_mode, regno);
if (rtx_insn *pat = targetm.gen_store_multiple (x, first,
GEN_INT (nregs)))
{
emit_insn (pat);
return;
......@@ -1547,7 +1541,7 @@ move_block_from_reg (int regno, rtx x, int nregs)
delete_insns_since (last);
}
for (i = 0; i < nregs; i++)
for (int i = 0; i < nregs; i++)
{
rtx tem = operand_subword (x, i, 1, BLKmode);
......
......@@ -32,6 +32,7 @@
Instructions should be documented in md.texi rather than here. */
DEF_TARGET_INSN (canonicalize_funcptr_for_compare, (rtx x0, rtx x1))
DEF_TARGET_INSN (epilogue, (void))
DEF_TARGET_INSN (load_multiple, (rtx x0, rtx x1, rtx x2))
DEF_TARGET_INSN (mem_signal_fence, (rtx x0))
DEF_TARGET_INSN (mem_thread_fence, (rtx x0))
DEF_TARGET_INSN (memory_barrier, (void))
......@@ -39,3 +40,4 @@ DEF_TARGET_INSN (prologue, (void))
DEF_TARGET_INSN (return, (void))
DEF_TARGET_INSN (sibcall_epilogue, (void))
DEF_TARGET_INSN (simple_return, (void))
DEF_TARGET_INSN (store_multiple, (rtx x0, rtx x1, rtx x2))
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