Commit 2062c40c by Jakub Jelinek Committed by Jakub Jelinek

re PR target/84844 (ICE in extract_constrain_insn_cached, at recog.c:2217…

re PR target/84844 (ICE in extract_constrain_insn_cached, at recog.c:2217 (error: insn does not satisfy its constraints))

	PR target/84844
	Revert
	2017-04-20  Uros Bizjak  <ubizjak@gmail.com>

	PR target/78090
	* config/i386/constraints.md (Yc): New register constraint.
	* config/i386/i386.md (*float<SWI48:mode><MODEF:mode>2_mixed):
	Use Yc constraint for alternative 2 of operand 0.  Remove
	preferred_for_speed attribute.

	* gcc.target/i386/pr84844.c: New test.

From-SVN: r258515
parent ec64ffc8
2018-03-14 Jakub Jelinek <jakub@redhat.com>
PR target/84844
Revert
2017-04-20 Uros Bizjak <ubizjak@gmail.com>
PR target/78090
* config/i386/constraints.md (Yc): New register constraint.
* config/i386/i386.md (*float<SWI48:mode><MODEF:mode>2_mixed):
Use Yc constraint for alternative 2 of operand 0. Remove
preferred_for_speed attribute.
2018-03-14 Richard Biener <rguenther@suse.de> 2018-03-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/84830 PR tree-optimization/84830
......
...@@ -99,7 +99,6 @@ ...@@ -99,7 +99,6 @@
;; We use the Y prefix to denote any number of conditional register sets: ;; We use the Y prefix to denote any number of conditional register sets:
;; z First SSE register. ;; z First SSE register.
;; c SSE inter-unit conversions enabled
;; i SSE2 inter-unit moves to SSE register enabled ;; i SSE2 inter-unit moves to SSE register enabled
;; j SSE2 inter-unit moves from SSE register enabled ;; j SSE2 inter-unit moves from SSE register enabled
;; d any EVEX encodable SSE register for AVX512BW target or any SSE register ;; d any EVEX encodable SSE register for AVX512BW target or any SSE register
...@@ -124,10 +123,6 @@ ...@@ -124,10 +123,6 @@
(define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS" (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
"First SSE register (@code{%xmm0}).") "First SSE register (@code{%xmm0}).")
(define_register_constraint "Yc"
"TARGET_SSE && TARGET_INTER_UNIT_CONVERSIONS ? ALL_SSE_REGS : NO_REGS"
"@internal Any SSE register, when SSE and inter-unit conversions are enabled.")
(define_register_constraint "Yi" (define_register_constraint "Yi"
"TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS" "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS"
"@internal Any SSE register, when SSE2 and inter-unit moves to vector registers are enabled.") "@internal Any SSE register, when SSE2 and inter-unit moves to vector registers are enabled.")
......
...@@ -5325,7 +5325,7 @@ ...@@ -5325,7 +5325,7 @@
}) })
(define_insn "*float<SWI48:mode><MODEF:mode>2_mixed" (define_insn "*float<SWI48:mode><MODEF:mode>2_mixed"
[(set (match_operand:MODEF 0 "register_operand" "=f,Yc,v") [(set (match_operand:MODEF 0 "register_operand" "=f,v,v")
(float:MODEF (float:MODEF
(match_operand:SWI48 1 "nonimmediate_operand" "m,r,m")))] (match_operand:SWI48 1 "nonimmediate_operand" "m,r,m")))]
"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH" "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH"
...@@ -5354,6 +5354,10 @@ ...@@ -5354,6 +5354,10 @@
&& X87_ENABLE_FLOAT (<MODEF:MODE>mode, && X87_ENABLE_FLOAT (<MODEF:MODE>mode,
<SWI48:MODE>mode)") <SWI48:MODE>mode)")
] ]
(symbol_ref "true")))
(set (attr "preferred_for_speed")
(cond [(eq_attr "alternative" "1")
(symbol_ref "TARGET_INTER_UNIT_CONVERSIONS")]
(symbol_ref "true")))]) (symbol_ref "true")))])
(define_insn "*float<SWI48x:mode><MODEF:mode>2_i387" (define_insn "*float<SWI48x:mode><MODEF:mode>2_i387"
......
2018-03-14 Jakub Jelinek <jakub@redhat.com>
PR target/84844
* gcc.target/i386/pr84844.c: New test.
2018-03-14 Richard Biener <rguenther@suse.de> 2018-03-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/84830 PR tree-optimization/84830
......
/* PR target/84844 */
/* { dg-do compile } */
/* { dg-options "-march=bdver1 -O2 -fschedule-insns -fselective-scheduling" } */
double
foo (int *x, int y, int z)
{
*x = y;
return z;
}
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