Skip to content

R
riscv-gcc-1
Commit 1ffcdc02 by H.J. Lu Committed by H.J. Lu
Options

i386.md: Remove trailing white spaces. 

2008-10-07  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/i386.md: Remove trailing white spaces.

From-SVN: r140962
parent beb0c9cc
Showing with 10 additions and 6 deletions
gcc/ChangeLog
2008-10-07 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/i386.md: Remove trailing white spaces.
2008-10-07 Kenneth Zadeck <zadeck@naturalbridge.com> 2008-10-07 Kenneth Zadeck <zadeck@naturalbridge.com>
PR rtl-optimization/37448 PR rtl-optimization/37448
......
gcc/config/i386/i386.md
...@@ -2559,14 +2559,14 @@ ...@@ -2559,14 +2559,14 @@
to stack may result in unaligned memory access. */ to stack may result in unaligned memory access. */
if (misaligned_operand (operands[0], TImode) if (misaligned_operand (operands[0], TImode)
|| misaligned_operand (operands[1], TImode)) || misaligned_operand (operands[1], TImode))
{ {
if (get_attr_mode (insn) == MODE_V4SF) if (get_attr_mode (insn) == MODE_V4SF)
return "%vmovups\t{%1, %0|%0, %1}"; return "%vmovups\t{%1, %0|%0, %1}";
else else
return "%vmovdqu\t{%1, %0|%0, %1}"; return "%vmovdqu\t{%1, %0|%0, %1}";
} }
else else
{ {
if (get_attr_mode (insn) == MODE_V4SF) if (get_attr_mode (insn) == MODE_V4SF)
return "%vmovaps\t{%1, %0|%0, %1}"; return "%vmovaps\t{%1, %0|%0, %1}";
else else
...@@ -2610,14 +2610,14 @@ ...@@ -2610,14 +2610,14 @@
to stack may result in unaligned memory access. */ to stack may result in unaligned memory access. */
if (misaligned_operand (operands[0], TImode) if (misaligned_operand (operands[0], TImode)
|| misaligned_operand (operands[1], TImode)) || misaligned_operand (operands[1], TImode))
{ {
if (get_attr_mode (insn) == MODE_V4SF) if (get_attr_mode (insn) == MODE_V4SF)
return "%vmovups\t{%1, %0|%0, %1}"; return "%vmovups\t{%1, %0|%0, %1}";
else else
return "%vmovdqu\t{%1, %0|%0, %1}"; return "%vmovdqu\t{%1, %0|%0, %1}";
} }
else else
{ {
if (get_attr_mode (insn) == MODE_V4SF) if (get_attr_mode (insn) == MODE_V4SF)
return "%vmovaps\t{%1, %0|%0, %1}"; return "%vmovaps\t{%1, %0|%0, %1}";
else else
...@@ -5150,8 +5150,8 @@ ...@@ -5150,8 +5150,8 @@
/* Avoid store forwarding (partial memory) stall penalty /* Avoid store forwarding (partial memory) stall penalty
by passing DImode value through XMM registers. */ by passing DImode value through XMM registers. */
if (<SSEMODEI24:MODE>mode == DImode && !TARGET_64BIT if (<SSEMODEI24:MODE>mode == DImode && !TARGET_64BIT
&& TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES && TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
&& optimize_function_for_speed_p (cfun)) && optimize_function_for_speed_p (cfun))
{ {
emit_insn (gen_floatdi<X87MODEF:mode>2_i387_with_xmm (operands[0], emit_insn (gen_floatdi<X87MODEF:mode>2_i387_with_xmm (operands[0],
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment