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Commit 1fa754dc by Alan Lawrence Committed by Alan Lawrence
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[ARM/AArch64 Testsuite] Add float16 tests to advsimd-intrinsics testsuite 

	* gcc.target/aarch64/advsimd-intrinsics/advsimd-intrinsics.exp:
	Set additional_flags for neon-fp16 if supported, else fallback to neon.

	* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
	(hfloat16_t): New.
	(result, expected, clean_results, DECL_VARIABLE_64BITS_VARIANTS,
	DECL_VARIABLE_128BITS_VARIANTS): Add float16x4_t and float16x8_t cases
	if supported.
	(CHECK_RESULTS): Redefine using CHECK_RESULTS_NAMED.
	(CHECK_RESULTS_NAMED): Move body to CHECK_RESULTS_NAMED_NO_FP16;
	redefine in terms of CHECK_RESULTS_NAMED_NO_FP16 with float16 variants
	when those are supported.
	(CHECK_RESULTS_NAMED_NO_FP16, CHECK_RESULTS_NO_FP16): New.
	(vdup_n_f16): New.

	* gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h (buffer,
	buffer_pad, buffer_dup, buffer_dup_pad): Add float16x4 and float16x8_t
	cases if supported.

	* gcc.target/aarch64/advsimd-intrinsics/vbsl.c (exec_vbsl):
	Use CHECK_RESULTS_NO_FP16 in place of CHECK_RESULTS.
	* gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c (exec_vdup_vmov):
	Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c (exec_vdup_lane):
	Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vext.c (exec_vext): Likewise.

	* gcc.target/aarch64/advsimd-intrinsics/vcombine.c (expected):
	Add float16x8_t case.
	(main, exec_vcombine): test float16x4_t -> float16x8_t, if supported.
	* gcc.target/aarch64/advsimd-intrinsics/vcreate.c (expected,
	main, exec_vcreate): Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vget_high (expected,
	 exec_vget_high): Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vget_low.c (expected,
	exec_vget_low): Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld1.c (expected, exec_vld1):
	Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld1_dup.c (expected,
	exec_vld1_dup): Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c (expected,
	exec_vld1_lane): Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vldX.c (expected, exec_vldX):
	Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c (expected,
	exec_vldX_dup): Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c (expected,
	exec_vldX_lane): Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vset_lane.c (expected,
	exec_vset_lane): Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c (expected,
	 exec_vst1_lane): Likewise.

From-SVN: r227554
parent 97973457
Showing with 328 additions and 48 deletions
gcc/testsuite/ChangeLog
2015-09-08 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/advsimd-intrinsics.exp:
Set additional_flags for neon-fp16 if supported, else fallback to neon.
* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
(hfloat16_t): New.
(result, expected, clean_results, DECL_VARIABLE_64BITS_VARIANTS,
DECL_VARIABLE_128BITS_VARIANTS): Add float16x4_t and float16x8_t cases
if supported.
(CHECK_RESULTS): Redefine using CHECK_RESULTS_NAMED.
(CHECK_RESULTS_NAMED): Move body to CHECK_RESULTS_NAMED_NO_FP16;
redefine in terms of CHECK_RESULTS_NAMED_NO_FP16 with float16 variants
when those are supported.
(CHECK_RESULTS_NAMED_NO_FP16, CHECK_RESULTS_NO_FP16): New.
(vdup_n_f16): New.
* gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h (buffer,
buffer_pad, buffer_dup, buffer_dup_pad): Add float16x4 and float16x8_t
cases if supported.
* gcc.target/aarch64/advsimd-intrinsics/vbsl.c (exec_vbsl):
Use CHECK_RESULTS_NO_FP16 in place of CHECK_RESULTS.
* gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c (exec_vdup_vmov):
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c (exec_vdup_lane):
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vext.c (exec_vext): Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vcombine.c (expected):
Add float16x8_t case.
(main, exec_vcombine): test float16x4_t -> float16x8_t, if supported.
* gcc.target/aarch64/advsimd-intrinsics/vcreate.c (expected,
main, exec_vcreate): Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vget_high (expected,
exec_vget_high): Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vget_low.c (expected,
exec_vget_low): Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vld1.c (expected, exec_vld1):
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vld1_dup.c (expected,
exec_vld1_dup): Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c (expected,
exec_vld1_lane): Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vldX.c (expected, exec_vldX):
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c (expected,
exec_vldX_dup): Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c (expected,
exec_vldX_lane): Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vset_lane.c (expected,
exec_vset_lane): Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c (expected,
exec_vst1_lane): Likewise.
2015-09-08 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/vget_high_1.c: Add float16x8->float16x4 case.
* gcc.target/aarch64/vget_low_1.c: Likewise.
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/advsimd-intrinsics.exp
......@@ -52,8 +52,12 @@ if {[istarget arm*-*-*]} then {
torture-init
set-torture-options $C_TORTURE_OPTIONS {{}} $LTO_TORTURE_OPTIONS
# Make sure Neon flags are provided, if necessary.
set additional_flags [add_options_for_arm_neon ""]
# Make sure Neon flags are provided, if necessary. Use fp16 if we can.
if {[check_effective_target_arm_neon_fp16_ok]} then {
set additional_flags [add_options_for_arm_neon_fp16 ""]
} else {
set additional_flags [add_options_for_arm_neon ""]
}
# Main loop.
gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.c]] \
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
......@@ -7,6 +7,7 @@
#include <inttypes.h>
/* helper type, to help write floating point results in integer form. */
typedef uint16_t hfloat16_t;
typedef uint32_t hfloat32_t;
typedef uint64_t hfloat64_t;
......@@ -132,6 +133,9 @@ static ARRAY(result, uint, 32, 2);
static ARRAY(result, uint, 64, 1);
static ARRAY(result, poly, 8, 8);
static ARRAY(result, poly, 16, 4);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
static ARRAY(result, float, 16, 4);
#endif
static ARRAY(result, float, 32, 2);
static ARRAY(result, int, 8, 16);
static ARRAY(result, int, 16, 8);
......@@ -143,6 +147,9 @@ static ARRAY(result, uint, 32, 4);
static ARRAY(result, uint, 64, 2);
static ARRAY(result, poly, 8, 16);
static ARRAY(result, poly, 16, 8);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
static ARRAY(result, float, 16, 8);
#endif
static ARRAY(result, float, 32, 4);
#ifdef __aarch64__
static ARRAY(result, float, 64, 2);
......@@ -160,6 +167,7 @@ extern ARRAY(expected, uint, 32, 2);
extern ARRAY(expected, uint, 64, 1);
extern ARRAY(expected, poly, 8, 8);
extern ARRAY(expected, poly, 16, 4);
extern ARRAY(expected, hfloat, 16, 4);
extern ARRAY(expected, hfloat, 32, 2);
extern ARRAY(expected, int, 8, 16);
extern ARRAY(expected, int, 16, 8);
......@@ -171,38 +179,11 @@ extern ARRAY(expected, uint, 32, 4);
extern ARRAY(expected, uint, 64, 2);
extern ARRAY(expected, poly, 8, 16);
extern ARRAY(expected, poly, 16, 8);
extern ARRAY(expected, hfloat, 16, 8);
extern ARRAY(expected, hfloat, 32, 4);
extern ARRAY(expected, hfloat, 64, 2);
/* Check results. Operates on all possible vector types. */
#define CHECK_RESULTS(test_name,comment) \
{ \
CHECK(test_name, int, 8, 8, PRIx8, expected, comment); \
CHECK(test_name, int, 16, 4, PRIx16, expected, comment); \
CHECK(test_name, int, 32, 2, PRIx32, expected, comment); \
CHECK(test_name, int, 64, 1, PRIx64, expected, comment); \
CHECK(test_name, uint, 8, 8, PRIx8, expected, comment); \
CHECK(test_name, uint, 16, 4, PRIx16, expected, comment); \
CHECK(test_name, uint, 32, 2, PRIx32, expected, comment); \
CHECK(test_name, uint, 64, 1, PRIx64, expected, comment); \
CHECK(test_name, poly, 8, 8, PRIx8, expected, comment); \
CHECK(test_name, poly, 16, 4, PRIx16, expected, comment); \
CHECK_FP(test_name, float, 32, 2, PRIx32, expected, comment); \
\
CHECK(test_name, int, 8, 16, PRIx8, expected, comment); \
CHECK(test_name, int, 16, 8, PRIx16, expected, comment); \
CHECK(test_name, int, 32, 4, PRIx32, expected, comment); \
CHECK(test_name, int, 64, 2, PRIx64, expected, comment); \
CHECK(test_name, uint, 8, 16, PRIx8, expected, comment); \
CHECK(test_name, uint, 16, 8, PRIx16, expected, comment); \
CHECK(test_name, uint, 32, 4, PRIx32, expected, comment); \
CHECK(test_name, uint, 64, 2, PRIx64, expected, comment); \
CHECK(test_name, poly, 8, 16, PRIx8, expected, comment); \
CHECK(test_name, poly, 16, 8, PRIx16, expected, comment); \
CHECK_FP(test_name, float, 32, 4, PRIx32, expected, comment); \
} \
#define CHECK_RESULTS_NAMED(test_name,EXPECTED,comment) \
#define CHECK_RESULTS_NAMED_NO_FP16(test_name,EXPECTED,comment) \
{ \
CHECK(test_name, int, 8, 8, PRIx8, EXPECTED, comment); \
CHECK(test_name, int, 16, 4, PRIx16, EXPECTED, comment); \
......@@ -229,6 +210,24 @@ extern ARRAY(expected, hfloat, 64, 2);
CHECK_FP(test_name, float, 32, 4, PRIx32, EXPECTED, comment); \
} \
/* Check results against EXPECTED. Operates on all possible vector types. */
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
#define CHECK_RESULTS_NAMED(test_name,EXPECTED,comment) \
{ \
CHECK_RESULTS_NAMED_NO_FP16(test_name, EXPECTED, comment) \
CHECK_FP(test_name, float, 16, 4, PRIx16, EXPECTED, comment); \
CHECK_FP(test_name, float, 16, 8, PRIx16, EXPECTED, comment); \
}
#else
#define CHECK_RESULTS_NAMED(test_name,EXPECTED,comment) \
CHECK_RESULTS_NAMED_NO_FP16(test_name, EXPECTED, comment)
#endif
#define CHECK_RESULTS_NO_FP16(test_name,comment) \
CHECK_RESULTS_NAMED_NO_FP16(test_name, expected, comment)
#define CHECK_RESULTS(test_name,comment) \
CHECK_RESULTS_NAMED(test_name, expected, comment)
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
......@@ -380,6 +379,9 @@ static void clean_results (void)
CLEAN(result, uint, 64, 1);
CLEAN(result, poly, 8, 8);
CLEAN(result, poly, 16, 4);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
CLEAN(result, float, 16, 4);
#endif
CLEAN(result, float, 32, 2);
CLEAN(result, int, 8, 16);
......@@ -392,6 +394,9 @@ static void clean_results (void)
CLEAN(result, uint, 64, 2);
CLEAN(result, poly, 8, 16);
CLEAN(result, poly, 16, 8);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
CLEAN(result, float, 16, 8);
#endif
CLEAN(result, float, 32, 4);
#if defined(__aarch64__)
......@@ -443,21 +448,40 @@ static void clean_results (void)
DECL_VARIABLE(VAR, uint, 64, 2)
/* Declare all 64 bits variants. */
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
#define DECL_VARIABLE_64BITS_VARIANTS(VAR) \
DECL_VARIABLE_64BITS_SIGNED_VARIANTS(VAR); \
DECL_VARIABLE_64BITS_UNSIGNED_VARIANTS(VAR); \
DECL_VARIABLE(VAR, poly, 8, 8); \
DECL_VARIABLE(VAR, poly, 16, 4); \
DECL_VARIABLE(VAR, float, 16, 4); \
DECL_VARIABLE(VAR, float, 32, 2)
#else
#define DECL_VARIABLE_64BITS_VARIANTS(VAR) \
DECL_VARIABLE_64BITS_SIGNED_VARIANTS(VAR); \
DECL_VARIABLE_64BITS_UNSIGNED_VARIANTS(VAR); \
DECL_VARIABLE(VAR, poly, 8, 8); \
DECL_VARIABLE(VAR, poly, 16, 4); \
DECL_VARIABLE(VAR, float, 32, 2)
#endif
/* Declare all 128 bits variants. */
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
#define DECL_VARIABLE_128BITS_VARIANTS(VAR) \
DECL_VARIABLE_128BITS_SIGNED_VARIANTS(VAR); \
DECL_VARIABLE_128BITS_UNSIGNED_VARIANTS(VAR); \
DECL_VARIABLE(VAR, poly, 8, 16); \
DECL_VARIABLE(VAR, poly, 16, 8); \
DECL_VARIABLE(VAR, float, 16, 8); \
DECL_VARIABLE(VAR, float, 32, 4)
#else
#define DECL_VARIABLE_128BITS_VARIANTS(VAR) \
DECL_VARIABLE_128BITS_SIGNED_VARIANTS(VAR); \
DECL_VARIABLE_128BITS_UNSIGNED_VARIANTS(VAR); \
DECL_VARIABLE(VAR, poly, 8, 16); \
DECL_VARIABLE(VAR, poly, 16, 8); \
DECL_VARIABLE(VAR, float, 32, 4)
#endif
/* Declare all variants. */
#define DECL_VARIABLE_ALL_VARIANTS(VAR) \
DECL_VARIABLE_64BITS_VARIANTS(VAR); \
......@@ -476,6 +500,15 @@ static void clean_results (void)
/* Helpers to initialize vectors. */
#define VDUP(VAR, Q, T1, T2, W, N, V) \
VECT_VAR(VAR, T1, W, N) = vdup##Q##_n_##T2##W(V)
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
/* Work around that there is no vdup_n_f16 intrinsic. */
#define vdup_n_f16(VAL) \
__extension__ \
({ \
float16_t f = VAL; \
vld1_dup_f16(&f); \
})
#endif
#define VSET_LANE(VAR, Q, T1, T2, W, N, L, V) \
VECT_VAR(VAR, T1, W, N) = vset##Q##_lane_##T2##W(V, \
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h
......@@ -118,6 +118,10 @@ VECT_VAR_DECL_INIT(buffer, uint, 32, 2);
PAD(buffer_pad, uint, 32, 2);
VECT_VAR_DECL_INIT(buffer, uint, 64, 1);
PAD(buffer_pad, uint, 64, 1);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
VECT_VAR_DECL_INIT(buffer, float, 16, 4);
PAD(buffer_pad, float, 16, 4);
#endif
VECT_VAR_DECL_INIT(buffer, float, 32, 2);
PAD(buffer_pad, float, 32, 2);
VECT_VAR_DECL_INIT(buffer, int, 8, 16);
......@@ -140,6 +144,10 @@ VECT_VAR_DECL_INIT(buffer, poly, 8, 16);
PAD(buffer_pad, poly, 8, 16);
VECT_VAR_DECL_INIT(buffer, poly, 16, 8);
PAD(buffer_pad, poly, 16, 8);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
VECT_VAR_DECL_INIT(buffer, float, 16, 8);
PAD(buffer_pad, float, 16, 8);
#endif
VECT_VAR_DECL_INIT(buffer, float, 32, 4);
PAD(buffer_pad, float, 32, 4);
#ifdef __aarch64__
......@@ -170,6 +178,10 @@ VECT_VAR_DECL_INIT(buffer_dup, poly, 8, 8);
VECT_VAR_DECL(buffer_dup_pad, poly, 8, 8);
VECT_VAR_DECL_INIT(buffer_dup, poly, 16, 4);
VECT_VAR_DECL(buffer_dup_pad, poly, 16, 4);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
VECT_VAR_DECL_INIT4(buffer_dup, float, 16, 4);
VECT_VAR_DECL(buffer_dup_pad, float, 16, 4);
#endif
VECT_VAR_DECL_INIT4(buffer_dup, float, 32, 2);
VECT_VAR_DECL(buffer_dup_pad, float, 32, 2);
......@@ -193,5 +205,9 @@ VECT_VAR_DECL_INIT(buffer_dup, poly, 8, 16);
VECT_VAR_DECL(buffer_dup_pad, poly, 8, 16);
VECT_VAR_DECL_INIT(buffer_dup, poly, 16, 8);
VECT_VAR_DECL(buffer_dup_pad, poly, 16, 8);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
VECT_VAR_DECL_INIT(buffer_dup, float, 16, 8);
VECT_VAR_DECL(buffer_dup_pad, float, 16, 8);
#endif
VECT_VAR_DECL_INIT(buffer_dup, float, 32, 4);
VECT_VAR_DECL(buffer_dup_pad, float, 32, 4);
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vbsl.c
......@@ -114,7 +114,7 @@ void exec_vbsl (void)
TEST_VBSL(uint, , float, f, 32, 2);
TEST_VBSL(uint, q, float, f, 32, 4);
CHECK_RESULTS (TEST_MSG, "");
CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
}
int main (void)
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcombine.c
......@@ -27,6 +27,8 @@ VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
0x66, 0x66, 0x66, 0x66 };
VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
0x40533333, 0x40533333 };
VECT_VAR_DECL(expected,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80,
0x4080, 0x4080, 0x4080, 0x4080 };
#define TEST_MSG "VCOMBINE"
void exec_vcombine (void)
......@@ -44,6 +46,9 @@ void exec_vcombine (void)
/* Initialize input "vector64_a" from "buffer". */
TEST_MACRO_64BITS_VARIANTS_2_5(VLOAD, vector64_a, buffer);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
VLOAD(vector64_a, buffer, , float, f, 16, 4);
#endif
VLOAD(vector64_a, buffer, , float, f, 32, 2);
/* Choose init value arbitrarily. */
......@@ -57,6 +62,9 @@ void exec_vcombine (void)
VDUP(vector64_b, , uint, u, 64, 1, 0x88);
VDUP(vector64_b, , poly, p, 8, 8, 0x55);
VDUP(vector64_b, , poly, p, 16, 4, 0x66);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
VDUP(vector64_b, , float, f, 16, 4, 2.25);
#endif
VDUP(vector64_b, , float, f, 32, 2, 3.3f);
clean_results ();
......@@ -72,6 +80,9 @@ void exec_vcombine (void)
TEST_VCOMBINE(uint, u, 64, 1, 2);
TEST_VCOMBINE(poly, p, 8, 8, 16);
TEST_VCOMBINE(poly, p, 16, 4, 8);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
TEST_VCOMBINE(float, f, 16, 4, 8);
#endif
TEST_VCOMBINE(float, f, 32, 2, 4);
CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, "");
......@@ -84,6 +95,9 @@ void exec_vcombine (void)
CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected, "");
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
#endif
CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
}
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcreate.c
......@@ -16,6 +16,7 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0x123456789abcdef0 };
VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0xde, 0xbc, 0x9a,
0x78, 0x56, 0x34, 0x12 };
VECT_VAR_DECL(expected,poly,16,4) [] = { 0xdef0, 0x9abc, 0x5678, 0x1234 };
VECT_VAR_DECL(expected,hfloat,16,4) [] = { 0xdef0, 0x9abc, 0x5678, 0x1234 };
VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x9abcdef0, 0x12345678 };
#define INSN_NAME vcreate
......@@ -38,6 +39,9 @@ FNNAME (INSN_NAME)
DECL_VAL(val, int, 16, 4);
DECL_VAL(val, int, 32, 2);
DECL_VAL(val, int, 64, 1);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
DECL_VAL(val, float, 16, 4);
#endif
DECL_VAL(val, float, 32, 2);
DECL_VAL(val, uint, 8, 8);
DECL_VAL(val, uint, 16, 4);
......@@ -50,6 +54,9 @@ FNNAME (INSN_NAME)
DECL_VARIABLE(vector_res, int, 16, 4);
DECL_VARIABLE(vector_res, int, 32, 2);
DECL_VARIABLE(vector_res, int, 64, 1);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
DECL_VARIABLE(vector_res, float, 16, 4);
#endif
DECL_VARIABLE(vector_res, float, 32, 2);
DECL_VARIABLE(vector_res, uint, 8, 8);
DECL_VARIABLE(vector_res, uint, 16, 4);
......@@ -65,6 +72,9 @@ FNNAME (INSN_NAME)
VECT_VAR(val, int, 16, 4) = 0x123456789abcdef0LL;
VECT_VAR(val, int, 32, 2) = 0x123456789abcdef0LL;
VECT_VAR(val, int, 64, 1) = 0x123456789abcdef0LL;
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
VECT_VAR(val, float, 16, 4) = 0x123456789abcdef0LL;
#endif
VECT_VAR(val, float, 32, 2) = 0x123456789abcdef0LL;
VECT_VAR(val, uint, 8, 8) = 0x123456789abcdef0ULL;
VECT_VAR(val, uint, 16, 4) = 0x123456789abcdef0ULL;
......@@ -76,6 +86,9 @@ FNNAME (INSN_NAME)
TEST_VCREATE(int, s, 8, 8);
TEST_VCREATE(int, s, 16, 4);
TEST_VCREATE(int, s, 32, 2);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
TEST_VCREATE(float, f, 16, 4);
#endif
TEST_VCREATE(float, f, 32, 2);
TEST_VCREATE(int, s, 64, 1);
TEST_VCREATE(uint, u, 8, 8);
......@@ -95,6 +108,9 @@ FNNAME (INSN_NAME)
CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, "");
CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected, "");
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
#endif
CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
}
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c
......@@ -187,13 +187,13 @@ void exec_vdup_vmov (void)
switch (i) {
case 0:
CHECK_RESULTS_NAMED (TEST_MSG, expected0, "");
CHECK_RESULTS_NAMED_NO_FP16 (TEST_MSG, expected0, "");
break;
case 1:
CHECK_RESULTS_NAMED (TEST_MSG, expected1, "");
CHECK_RESULTS_NAMED_NO_FP16 (TEST_MSG, expected1, "");
break;
case 2:
CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
CHECK_RESULTS_NAMED_NO_FP16 (TEST_MSG, expected2, "");
break;
default:
abort();
......@@ -232,13 +232,13 @@ void exec_vdup_vmov (void)
switch (i) {
case 0:
CHECK_RESULTS_NAMED (TEST_MSG, expected0, "");
CHECK_RESULTS_NAMED_NO_FP16 (TEST_MSG, expected0, "");
break;
case 1:
CHECK_RESULTS_NAMED (TEST_MSG, expected1, "");
CHECK_RESULTS_NAMED_NO_FP16 (TEST_MSG, expected1, "");
break;
case 2:
CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
CHECK_RESULTS_NAMED_NO_FP16 (TEST_MSG, expected2, "");
break;
default:
abort();
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c
......@@ -90,7 +90,7 @@ void exec_vdup_lane (void)
TEST_VDUP_LANE(q, poly, p, 16, 8, 4, 1);
TEST_VDUP_LANE(q, float, f, 32, 4, 2, 1);
CHECK_RESULTS (TEST_MSG, "");
CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
}
int main (void)
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vext.c
......@@ -113,7 +113,7 @@ void exec_vext (void)
TEST_VEXT(q, poly, p, 16, 8, 6);
TEST_VEXT(q, float, f, 32, 4, 3);
CHECK_RESULTS (TEST_MSG, "");
CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
}
int main (void)
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_high.c
......@@ -16,6 +16,7 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff1 };
VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf8, 0xf9, 0xfa, 0xfb,
0xfc, 0xfd, 0xfe, 0xff };
VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
VECT_VAR_DECL(expected,hfloat,16,4) [] = { 0xca00, 0xc980, 0xc900, 0xc880 };
VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 };
#define TEST_MSG "VGET_HIGH"
......@@ -31,6 +32,9 @@ void exec_vget_high (void)
DECL_VARIABLE_128BITS_VARIANTS(vector128);
TEST_MACRO_128BITS_VARIANTS_2_5(VLOAD, vector128, buffer);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
VLOAD(vector128, buffer, q, float, f, 16, 8);
#endif
VLOAD(vector128, buffer, q, float, f, 32, 4);
clean_results ();
......@@ -46,6 +50,9 @@ void exec_vget_high (void)
TEST_VGET_HIGH(uint, u, 64, 1, 2);
TEST_VGET_HIGH(poly, p, 8, 8, 16);
TEST_VGET_HIGH(poly, p, 16, 4, 8);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
TEST_VGET_HIGH(float, f, 16, 4, 8);
#endif
TEST_VGET_HIGH(float, f, 32, 2, 4);
CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_low.c
......@@ -16,6 +16,7 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
0xf4, 0xf5, 0xf6, 0xf7 };
VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
VECT_VAR_DECL(expected,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
#define TEST_MSG "VGET_LOW"
......@@ -31,6 +32,9 @@ void exec_vget_low (void)
DECL_VARIABLE_128BITS_VARIANTS(vector128);
TEST_MACRO_128BITS_VARIANTS_2_5(VLOAD, vector128, buffer);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
VLOAD(vector128, buffer, q, float, f, 16, 8);
#endif
VLOAD(vector128, buffer, q, float, f, 32, 4);
clean_results ();
......@@ -46,6 +50,9 @@ void exec_vget_low (void)
TEST_VGET_LOW(uint, u, 64, 1, 2);
TEST_VGET_LOW(poly, p, 8, 8, 16);
TEST_VGET_LOW(poly, p, 16, 4, 8);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
TEST_VGET_LOW(float, f, 16, 4, 8);
#endif
TEST_VGET_LOW(float, f, 32, 2, 4);
CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
......@@ -58,6 +65,9 @@ void exec_vget_low (void)
CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, "");
CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected, "");
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
#endif
CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
}
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1.c
......@@ -16,6 +16,7 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
0xf4, 0xf5, 0xf6, 0xf7 };
VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
VECT_VAR_DECL(expected,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
0xf4, 0xf5, 0xf6, 0xf7,
......@@ -44,6 +45,8 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
0xfc, 0xfd, 0xfe, 0xff };
VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
0xfff4, 0xfff5, 0xfff6, 0xfff7 };
VECT_VAR_DECL(expected,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80,
0xca00, 0xc980, 0xc900, 0xc880 };
VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
0xc1600000, 0xc1500000 };
......@@ -62,6 +65,10 @@ void exec_vld1 (void)
TEST_MACRO_ALL_VARIANTS_2_5(TEST_VLD1, vector, buffer);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
TEST_VLD1(vector, buffer, , float, f, 16, 4);
TEST_VLD1(vector, buffer, q, float, f, 16, 8);
#endif
TEST_VLD1(vector, buffer, , float, f, 32, 2);
TEST_VLD1(vector, buffer, q, float, f, 32, 4);
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_dup.c
......@@ -17,6 +17,7 @@ VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 };
VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0,
0xf0, 0xf0, 0xf0, 0xf0 };
VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff0, 0xfff0, 0xfff0 };
VECT_VAR_DECL(expected0,hfloat,16,4) [] = { 0xcc00, 0xcc00, 0xcc00, 0xcc00 };
VECT_VAR_DECL(expected0,hfloat,32,2) [] = { 0xc1800000, 0xc1800000 };
VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0,
0xf0, 0xf0, 0xf0, 0xf0,
......@@ -44,6 +45,8 @@ VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0,
0xf0, 0xf0, 0xf0, 0xf0 };
VECT_VAR_DECL(expected0,poly,16,8) [] = { 0xfff0, 0xfff0, 0xfff0, 0xfff0,
0xfff0, 0xfff0, 0xfff0, 0xfff0 };
VECT_VAR_DECL(expected0,hfloat,16,8) [] = { 0xcc00, 0xcc00, 0xcc00, 0xcc00,
0xcc00, 0xcc00, 0xcc00, 0xcc00 };
VECT_VAR_DECL(expected0,hfloat,32,4) [] = { 0xc1800000, 0xc1800000,
0xc1800000, 0xc1800000 };
......@@ -61,6 +64,7 @@ VECT_VAR_DECL(expected1,uint,64,1) [] = { 0xfffffffffffffff1 };
VECT_VAR_DECL(expected1,poly,8,8) [] = { 0xf1, 0xf1, 0xf1, 0xf1,
0xf1, 0xf1, 0xf1, 0xf1 };
VECT_VAR_DECL(expected1,poly,16,4) [] = { 0xfff1, 0xfff1, 0xfff1, 0xfff1 };
VECT_VAR_DECL(expected1,hfloat,16,4) [] = { 0xcb80, 0xcb80, 0xcb80, 0xcb80 };
VECT_VAR_DECL(expected1,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 };
VECT_VAR_DECL(expected1,int,8,16) [] = { 0xf1, 0xf1, 0xf1, 0xf1,
0xf1, 0xf1, 0xf1, 0xf1,
......@@ -88,6 +92,8 @@ VECT_VAR_DECL(expected1,poly,8,16) [] = { 0xf1, 0xf1, 0xf1, 0xf1,
0xf1, 0xf1, 0xf1, 0xf1 };
VECT_VAR_DECL(expected1,poly,16,8) [] = { 0xfff1, 0xfff1, 0xfff1, 0xfff1,
0xfff1, 0xfff1, 0xfff1, 0xfff1 };
VECT_VAR_DECL(expected1,hfloat,16,8) [] = { 0xcb80, 0xcb80, 0xcb80, 0xcb80,
0xcb80, 0xcb80, 0xcb80, 0xcb80 };
VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0xc1700000, 0xc1700000,
0xc1700000, 0xc1700000 };
......@@ -105,6 +111,7 @@ VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff2 };
VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf2, 0xf2, 0xf2, 0xf2,
0xf2, 0xf2, 0xf2, 0xf2 };
VECT_VAR_DECL(expected2,poly,16,4) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff2 };
VECT_VAR_DECL(expected2,hfloat,16,4) [] = { 0xcb00, 0xcb00, 0xcb00, 0xcb00 };
VECT_VAR_DECL(expected2,hfloat,32,2) [] = { 0xc1600000, 0xc1600000 };
VECT_VAR_DECL(expected2,int,8,16) [] = { 0xf2, 0xf2, 0xf2, 0xf2,
0xf2, 0xf2, 0xf2, 0xf2,
......@@ -132,6 +139,8 @@ VECT_VAR_DECL(expected2,poly,8,16) [] = { 0xf2, 0xf2, 0xf2, 0xf2,
0xf2, 0xf2, 0xf2, 0xf2 };
VECT_VAR_DECL(expected2,poly,16,8) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff2,
0xfff2, 0xfff2, 0xfff2, 0xfff2 };
VECT_VAR_DECL(expected2,hfloat,16,8) [] = { 0xcb00, 0xcb00, 0xcb00, 0xcb00,
0xcb00, 0xcb00, 0xcb00, 0xcb00 };
VECT_VAR_DECL(expected2,hfloat,32,4) [] = { 0xc1600000, 0xc1600000,
0xc1600000, 0xc1600000 };
......@@ -154,6 +163,10 @@ void exec_vld1_dup (void)
TEST_MACRO_ALL_VARIANTS_2_5(TEST_VLD1_DUP, vector, buffer_dup);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
TEST_VLD1_DUP(vector, buffer_dup, , float, f, 16, 4);
TEST_VLD1_DUP(vector, buffer_dup, q, float, f, 16, 8);
#endif
TEST_VLD1_DUP(vector, buffer_dup, , float, f, 32, 2);
TEST_VLD1_DUP(vector, buffer_dup, q, float, f, 32, 4);
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c
......@@ -16,6 +16,7 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
VECT_VAR_DECL(expected,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xf0 };
VECT_VAR_DECL(expected,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 };
VECT_VAR_DECL(expected,hfloat,16,4) [] = { 0xaaaa, 0xaaaa, 0xcc00, 0xaaaa };
VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xaaaaaaaa, 0xc1800000 };
VECT_VAR_DECL(expected,int,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa,
......@@ -43,6 +44,8 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
0xf0, 0xaa, 0xaa, 0xaa };
VECT_VAR_DECL(expected,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
0xaaaa, 0xaaaa, 0xfff0, 0xaaaa };
VECT_VAR_DECL(expected,hfloat,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
0xaaaa, 0xcc00, 0xaaaa, 0xaaaa };
VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
0xc1800000, 0xaaaaaaaa };
......@@ -72,6 +75,9 @@ void exec_vld1_lane (void)
ARRAY(buffer_src, uint, 64, 1);
ARRAY(buffer_src, poly, 8, 8);
ARRAY(buffer_src, poly, 16, 4);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
ARRAY(buffer_src, float, 16, 4);
#endif
ARRAY(buffer_src, float, 32, 2);
ARRAY(buffer_src, int, 8, 16);
......@@ -84,6 +90,9 @@ void exec_vld1_lane (void)
ARRAY(buffer_src, uint, 64, 2);
ARRAY(buffer_src, poly, 8, 16);
ARRAY(buffer_src, poly, 16, 8);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
ARRAY(buffer_src, float, 16, 8);
#endif
ARRAY(buffer_src, float, 32, 4);
clean_results ();
......@@ -99,6 +108,9 @@ void exec_vld1_lane (void)
TEST_VLD1_LANE(, uint, u, 64, 1, 0);
TEST_VLD1_LANE(, poly, p, 8, 8, 7);
TEST_VLD1_LANE(, poly, p, 16, 4, 3);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
TEST_VLD1_LANE(, float, f, 16, 4, 2);
#endif
TEST_VLD1_LANE(, float, f, 32, 2, 1);
TEST_VLD1_LANE(q, int, s, 8, 16, 15);
......@@ -111,6 +123,9 @@ void exec_vld1_lane (void)
TEST_VLD1_LANE(q, uint, u, 64, 2, 0);
TEST_VLD1_LANE(q, poly, p, 8, 16, 12);
TEST_VLD1_LANE(q, poly, p, 16, 8, 6);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
TEST_VLD1_LANE(q, float, f, 16, 8, 5);
#endif
TEST_VLD1_LANE(q, float, f, 32, 4, 2);
CHECK_RESULTS (TEST_MSG, "");
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
......@@ -18,6 +18,7 @@ VECT_VAR_DECL(expected_vld2_0,uint,64,1) [] = { 0xfffffffffffffff0 };
VECT_VAR_DECL(expected_vld2_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
0xf0, 0xf1, 0xf0, 0xf1 };
VECT_VAR_DECL(expected_vld2_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 };
VECT_VAR_DECL(expected_vld2_0,hfloat,16,4) [] = {0xcc00, 0xcb80, 0xcc00, 0xcb80 };
VECT_VAR_DECL(expected_vld2_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
/* vld2_dup/chunk 1. */
......@@ -35,6 +36,7 @@ VECT_VAR_DECL(expected_vld2_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
0xf0, 0xf1, 0xf0, 0xf1 };
VECT_VAR_DECL(expected_vld2_1,poly,16,4) [] = { 0xfff0, 0xfff1,
0xfff0, 0xfff1 };
VECT_VAR_DECL(expected_vld2_1,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcc00, 0xcb80 };
VECT_VAR_DECL(expected_vld2_1,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
/* vld3_dup/chunk 0. */
......@@ -54,6 +56,7 @@ VECT_VAR_DECL(expected_vld3_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf0,
0xf1, 0xf2, 0xf0, 0xf1 };
VECT_VAR_DECL(expected_vld3_0,poly,16,4) [] = { 0xfff0, 0xfff1,
0xfff2, 0xfff0 };
VECT_VAR_DECL(expected_vld3_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xcc00 };
VECT_VAR_DECL(expected_vld3_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
/* vld3_dup/chunk 1. */
......@@ -73,6 +76,7 @@ VECT_VAR_DECL(expected_vld3_1,poly,8,8) [] = { 0xf2, 0xf0, 0xf1, 0xf2,
0xf0, 0xf1, 0xf2, 0xf0 };
VECT_VAR_DECL(expected_vld3_1,poly,16,4) [] = { 0xfff1, 0xfff2,
0xfff0, 0xfff1 };
VECT_VAR_DECL(expected_vld3_1,hfloat,16,4) [] = { 0xcb80, 0xcb00, 0xcc00, 0xcb80 };
VECT_VAR_DECL(expected_vld3_1,hfloat,32,2) [] = { 0xc1600000, 0xc1800000 };
/* vld3_dup/chunk 2. */
......@@ -92,6 +96,7 @@ VECT_VAR_DECL(expected_vld3_2,poly,8,8) [] = { 0xf1, 0xf2, 0xf0, 0xf1,
0xf2, 0xf0, 0xf1, 0xf2 };
VECT_VAR_DECL(expected_vld3_2,poly,16,4) [] = { 0xfff2, 0xfff0,
0xfff1, 0xfff2 };
VECT_VAR_DECL(expected_vld3_2,hfloat,16,4) [] = { 0xcb00, 0xcc00, 0xcb80, 0xcb00 };
VECT_VAR_DECL(expected_vld3_2,hfloat,32,2) [] = { 0xc1700000, 0xc1600000 };
/* vld4_dup/chunk 0. */
......@@ -109,6 +114,7 @@ VECT_VAR_DECL(expected_vld4_0,uint,64,1) [] = { 0xfffffffffffffff0 };
VECT_VAR_DECL(expected_vld4_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
0xf0, 0xf1, 0xf2, 0xf3 };
VECT_VAR_DECL(expected_vld4_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
VECT_VAR_DECL(expected_vld4_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
VECT_VAR_DECL(expected_vld4_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
/* vld4_dup/chunk 1. */
......@@ -125,6 +131,7 @@ VECT_VAR_DECL(expected_vld4_1,uint,64,1) [] = { 0xfffffffffffffff1 };
VECT_VAR_DECL(expected_vld4_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
0xf0, 0xf1, 0xf2, 0xf3 };
VECT_VAR_DECL(expected_vld4_1,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
VECT_VAR_DECL(expected_vld4_1,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
VECT_VAR_DECL(expected_vld4_1,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 };
/* vld4_dup/chunk 2. */
......@@ -141,6 +148,7 @@ VECT_VAR_DECL(expected_vld4_2,uint,64,1) [] = { 0xfffffffffffffff2 };
VECT_VAR_DECL(expected_vld4_2,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
0xf0, 0xf1, 0xf2, 0xf3 };
VECT_VAR_DECL(expected_vld4_2,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
VECT_VAR_DECL(expected_vld4_2,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
VECT_VAR_DECL(expected_vld4_2,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
/* vld4_dup/chunk3. */
......@@ -157,6 +165,7 @@ VECT_VAR_DECL(expected_vld4_3,uint,64,1) [] = { 0xfffffffffffffff3 };
VECT_VAR_DECL(expected_vld4_3,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
0xf0, 0xf1, 0xf2, 0xf3 };
VECT_VAR_DECL(expected_vld4_3,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
VECT_VAR_DECL(expected_vld4_3,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
VECT_VAR_DECL(expected_vld4_3,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 };
void exec_vldX_dup (void)
......@@ -188,7 +197,7 @@ void exec_vldX_dup (void)
&(VECT_VAR(result_bis_##X, T1, W, N)[Y*N]), \
sizeof(VECT_VAR(result, T1, W, N)));
#define DECL_ALL_VLDX_DUP(X) \
#define DECL_ALL_VLDX_DUP_NO_FP16(X) \
DECL_VLDX_DUP(int, 8, 8, X); \
DECL_VLDX_DUP(int, 16, 4, X); \
DECL_VLDX_DUP(int, 32, 2, X); \
......@@ -201,7 +210,15 @@ void exec_vldX_dup (void)
DECL_VLDX_DUP(poly, 16, 4, X); \
DECL_VLDX_DUP(float, 32, 2, X)
#define TEST_ALL_VLDX_DUP(X) \
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
#define DECL_ALL_VLDX_DUP(X) \
DECL_ALL_VLDX_DUP_NO_FP16(X); \
DECL_VLDX_DUP(float, 16, 4, X)
#else
#define DECL_ALL_VLDX_DUP(X) DECL_ALL_VLDX_DUP_NO_FP16(X)
#endif
#define TEST_ALL_VLDX_DUP_NO_FP16(X) \
TEST_VLDX_DUP(, int, s, 8, 8, X); \
TEST_VLDX_DUP(, int, s, 16, 4, X); \
TEST_VLDX_DUP(, int, s, 32, 2, X); \
......@@ -214,7 +231,15 @@ void exec_vldX_dup (void)
TEST_VLDX_DUP(, poly, p, 16, 4, X); \
TEST_VLDX_DUP(, float, f, 32, 2, X)
#define TEST_ALL_EXTRA_CHUNKS(X, Y) \
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
#define TEST_ALL_VLDX_DUP(X) \
TEST_ALL_VLDX_DUP_NO_FP16(X); \
TEST_VLDX_DUP(, float, f, 16, 4, X)
#else
#define TEST_ALL_VLDX_DUP(X) TEST_ALL_VLDX_DUP_NO_FP16(X)
#endif
#define TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y) \
TEST_EXTRA_CHUNK(int, 8, 8, X, Y); \
TEST_EXTRA_CHUNK(int, 16, 4, X, Y); \
TEST_EXTRA_CHUNK(int, 32, 2, X, Y); \
......@@ -227,9 +252,16 @@ void exec_vldX_dup (void)
TEST_EXTRA_CHUNK(poly, 16, 4, X, Y); \
TEST_EXTRA_CHUNK(float, 32, 2, X, Y)
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
#define TEST_ALL_EXTRA_CHUNKS(X, Y) \
TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y); \
TEST_EXTRA_CHUNK(float, 16, 4, X, Y)
#else
#define TEST_ALL_EXTRA_CHUNKS(X, Y) TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y)
#endif
/* vldX_dup supports only 64-bit inputs. */
#define CHECK_RESULTS_VLDX_DUP(test_name,EXPECTED,comment) \
{ \
#define CHECK_RESULTS_VLDX_DUP_NO_FP16(test_name,EXPECTED,comment) \
CHECK(test_name, int, 8, 8, PRIx8, EXPECTED, comment); \
CHECK(test_name, int, 16, 4, PRIx16, EXPECTED, comment); \
CHECK(test_name, int, 32, 2, PRIx32, EXPECTED, comment); \
......@@ -240,8 +272,20 @@ void exec_vldX_dup (void)
CHECK(test_name, uint, 64, 1, PRIx64, EXPECTED, comment); \
CHECK(test_name, poly, 8, 8, PRIx8, EXPECTED, comment); \
CHECK(test_name, poly, 16, 4, PRIx16, EXPECTED, comment); \
CHECK_FP(test_name, float, 32, 2, PRIx32, EXPECTED, comment); \
} \
CHECK_FP(test_name, float, 32, 2, PRIx32, EXPECTED, comment)
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
#define CHECK_RESULTS_VLDX_DUP(test_name,EXPECTED,comment) \
{ \
CHECK_RESULTS_VLDX_DUP_NO_FP16(test_name,EXPECTED,comment); \
CHECK_FP(test_name, float, 16, 4, PRIx16, EXPECTED, comment); \
}
#else
#define CHECK_RESULTS_VLDX_DUP(test_name,EXPECTED,comment) \
{ \
CHECK_RESULTS_VLDX_DUP_NO_FP16(test_name,EXPECTED,comment); \
}
#endif
DECL_ALL_VLDX_DUP(2);
DECL_ALL_VLDX_DUP(3);
......@@ -269,6 +313,10 @@ void exec_vldX_dup (void)
PAD(buffer_vld2_pad, poly, 8, 8);
VECT_ARRAY_INIT2(buffer_vld2, poly, 16, 4);
PAD(buffer_vld2_pad, poly, 16, 4);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
VECT_ARRAY_INIT2(buffer_vld2, float, 16, 4);
PAD(buffer_vld2_pad, float, 16, 4);
#endif
VECT_ARRAY_INIT2(buffer_vld2, float, 32, 2);
PAD(buffer_vld2_pad, float, 32, 2);
......@@ -292,6 +340,10 @@ void exec_vldX_dup (void)
PAD(buffer_vld2_pad, poly, 8, 16);
VECT_ARRAY_INIT2(buffer_vld2, poly, 16, 8);
PAD(buffer_vld2_pad, poly, 16, 8);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
VECT_ARRAY_INIT2(buffer_vld2, float, 16, 8);
PAD(buffer_vld2_pad, float, 16, 8);
#endif
VECT_ARRAY_INIT2(buffer_vld2, float, 32, 4);
PAD(buffer_vld2_pad, float, 32, 4);
......@@ -316,6 +368,10 @@ void exec_vldX_dup (void)
PAD(buffer_vld3_pad, poly, 8, 8);
VECT_ARRAY_INIT3(buffer_vld3, poly, 16, 4);
PAD(buffer_vld3_pad, poly, 16, 4);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
VECT_ARRAY_INIT3(buffer_vld3, float, 16, 4);
PAD(buffer_vld3_pad, float, 16, 4);
#endif
VECT_ARRAY_INIT3(buffer_vld3, float, 32, 2);
PAD(buffer_vld3_pad, float, 32, 2);
......@@ -339,6 +395,10 @@ void exec_vldX_dup (void)
PAD(buffer_vld3_pad, poly, 8, 16);
VECT_ARRAY_INIT3(buffer_vld3, poly, 16, 8);
PAD(buffer_vld3_pad, poly, 16, 8);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
VECT_ARRAY_INIT3(buffer_vld3, float, 16, 8);
PAD(buffer_vld3_pad, float, 16, 8);
#endif
VECT_ARRAY_INIT3(buffer_vld3, float, 32, 4);
PAD(buffer_vld3_pad, float, 32, 4);
......@@ -363,6 +423,10 @@ void exec_vldX_dup (void)
PAD(buffer_vld4_pad, poly, 8, 8);
VECT_ARRAY_INIT4(buffer_vld4, poly, 16, 4);
PAD(buffer_vld4_pad, poly, 16, 4);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
VECT_ARRAY_INIT4(buffer_vld4, float, 16, 4);
PAD(buffer_vld4_pad, float, 16, 4);
#endif
VECT_ARRAY_INIT4(buffer_vld4, float, 32, 2);
PAD(buffer_vld4_pad, float, 32, 2);
......@@ -386,6 +450,10 @@ void exec_vldX_dup (void)
PAD(buffer_vld4_pad, poly, 8, 16);
VECT_ARRAY_INIT4(buffer_vld4, poly, 16, 8);
PAD(buffer_vld4_pad, poly, 16, 8);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
VECT_ARRAY_INIT4(buffer_vld4, float, 16, 8);
PAD(buffer_vld4_pad, float, 16, 8);
#endif
VECT_ARRAY_INIT4(buffer_vld4, float, 32, 4);
PAD(buffer_vld4_pad, float, 32, 4);
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vset_lane.c
......@@ -16,6 +16,7 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0x88 };
VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
0xf4, 0xf5, 0x55, 0xf7 };
VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0xfff1, 0x66, 0xfff3 };
VECT_VAR_DECL(expected,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0x4840, 0xca80 };
VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0x4204cccd };
VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
0xf4, 0xf5, 0xf6, 0xf7,
......@@ -41,6 +42,8 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
0xfc, 0xfd, 0xdd, 0xff };
VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
0xfff4, 0xfff5, 0xee, 0xfff7 };
VECT_VAR_DECL(expected,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80,
0xca00, 0x4480, 0xc900, 0xc880 };
VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
0xc1600000, 0x41333333 };
......@@ -61,6 +64,10 @@ void exec_vset_lane (void)
/* Initialize input "vector" from "buffer". */
TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
VLOAD(vector, buffer, , float, f, 16, 4);
VLOAD(vector, buffer, q, float, f, 16, 8);
#endif
VLOAD(vector, buffer, , float, f, 32, 2);
VLOAD(vector, buffer, q, float, f, 32, 4);
......@@ -75,6 +82,9 @@ void exec_vset_lane (void)
TEST_VSET_LANE(, uint, u, 64, 1, 0x88, 0);
TEST_VSET_LANE(, poly, p, 8, 8, 0x55, 6);
TEST_VSET_LANE(, poly, p, 16, 4, 0x66, 2);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
TEST_VSET_LANE(, float, f, 16, 4, 8.5f, 2);
#endif
TEST_VSET_LANE(, float, f, 32, 2, 33.2f, 1);
TEST_VSET_LANE(q, int, s, 8, 16, 0x99, 15);
......@@ -87,6 +97,9 @@ void exec_vset_lane (void)
TEST_VSET_LANE(q, uint, u, 64, 2, 0x11, 1);
TEST_VSET_LANE(q, poly, p, 8, 16, 0xDD, 14);
TEST_VSET_LANE(q, poly, p, 16, 8, 0xEE, 6);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
TEST_VSET_LANE(q, float, f, 16, 8, 4.5f, 5);
#endif
TEST_VSET_LANE(q, float, f, 32, 4, 11.2f, 3);
CHECK_RESULTS(TEST_MSG, "");
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c
......@@ -16,6 +16,7 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf6, 0x33, 0x33, 0x33,
0x33, 0x33, 0x33, 0x33 };
VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff2, 0x3333, 0x3333, 0x3333 };
VECT_VAR_DECL(expected,hfloat,16,4) [] = { 0xcb80, 0x3333, 0x3333, 0x3333 };
VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0x33333333 };
VECT_VAR_DECL(expected,int,8,16) [] = { 0xff, 0x33, 0x33, 0x33,
0x33, 0x33, 0x33, 0x33,
......@@ -42,6 +43,8 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0xfa, 0x33, 0x33, 0x33,
0x33, 0x33, 0x33, 0x33 };
VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff4, 0x3333, 0x3333, 0x3333,
0x3333, 0x3333, 0x3333, 0x3333 };
VECT_VAR_DECL(expected,hfloat,16,8) [] = { 0xc900, 0x3333, 0x3333, 0x3333,
0x3333, 0x3333, 0x3333, 0x3333 };
VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1700000, 0x33333333,
0x33333333, 0x33333333 };
......@@ -69,6 +72,9 @@ void exec_vst1_lane (void)
TEST_VST1_LANE(, uint, u, 64, 1, 0);
TEST_VST1_LANE(, poly, p, 8, 8, 6);
TEST_VST1_LANE(, poly, p, 16, 4, 2);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
TEST_VST1_LANE(, float, f, 16, 4, 1);
#endif
TEST_VST1_LANE(, float, f, 32, 2, 1);
TEST_VST1_LANE(q, int, s, 8, 16, 15);
......@@ -81,6 +87,9 @@ void exec_vst1_lane (void)
TEST_VST1_LANE(q, uint, u, 64, 2, 0);
TEST_VST1_LANE(q, poly, p, 8, 16, 10);
TEST_VST1_LANE(q, poly, p, 16, 8, 4);
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
TEST_VST1_LANE(q, float, f, 16, 8, 6);
#endif
TEST_VST1_LANE(q, float, f, 32, 4, 1);
CHECK_RESULTS(TEST_MSG, "");
......
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