Commit 1d6aee1c by Kyrylo Tkachov Committed by Kyrylo Tkachov

arm-fixed.md (ssmulsa3, usmulusa3): Adjust for arm_restrict_it.

2013-07-25  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm-fixed.md (ssmulsa3, usmulusa3):
	Adjust for arm_restrict_it.
	Remove trailing whitespace.

From-SVN: r201249
parent 017d38f5
2013-07-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm-fixed.md (ssmulsa3, usmulusa3):
Adjust for arm_restrict_it.
Remove trailing whitespace.
2013-07-25  Mark Kettenis  <kettenis@openbsd.org> 2013-07-25  Mark Kettenis  <kettenis@openbsd.org>
* config/pa/pa.c (pa_trampoline_init): Emit __enable_execute_stack * config/pa/pa.c (pa_trampoline_init): Emit __enable_execute_stack
......
...@@ -104,7 +104,7 @@ ...@@ -104,7 +104,7 @@
rtx tmp1 = gen_reg_rtx (HImode); rtx tmp1 = gen_reg_rtx (HImode);
rtx tmp2 = gen_reg_rtx (HImode); rtx tmp2 = gen_reg_rtx (HImode);
rtx tmp3 = gen_reg_rtx (SImode); rtx tmp3 = gen_reg_rtx (SImode);
emit_insn (gen_extendqihi2 (tmp1, gen_lowpart (QImode, operands[1]))); emit_insn (gen_extendqihi2 (tmp1, gen_lowpart (QImode, operands[1])));
emit_insn (gen_extendqihi2 (tmp2, gen_lowpart (QImode, operands[2]))); emit_insn (gen_extendqihi2 (tmp2, gen_lowpart (QImode, operands[2])));
emit_insn (gen_mulhisi3 (tmp3, tmp1, tmp2)); emit_insn (gen_mulhisi3 (tmp3, tmp1, tmp2));
...@@ -140,7 +140,7 @@ ...@@ -140,7 +140,7 @@
rtx tmp1 = gen_reg_rtx (DImode); rtx tmp1 = gen_reg_rtx (DImode);
rtx tmp2 = gen_reg_rtx (SImode); rtx tmp2 = gen_reg_rtx (SImode);
rtx tmp3 = gen_reg_rtx (SImode); rtx tmp3 = gen_reg_rtx (SImode);
/* s.31 * s.31 -> s.62 multiplication. */ /* s.31 * s.31 -> s.62 multiplication. */
emit_insn (gen_mulsidi3 (tmp1, gen_lowpart (SImode, operands[1]), emit_insn (gen_mulsidi3 (tmp1, gen_lowpart (SImode, operands[1]),
gen_lowpart (SImode, operands[2]))); gen_lowpart (SImode, operands[2])));
...@@ -162,7 +162,7 @@ ...@@ -162,7 +162,7 @@
rtx tmp1 = gen_reg_rtx (DImode); rtx tmp1 = gen_reg_rtx (DImode);
rtx tmp2 = gen_reg_rtx (SImode); rtx tmp2 = gen_reg_rtx (SImode);
rtx tmp3 = gen_reg_rtx (SImode); rtx tmp3 = gen_reg_rtx (SImode);
emit_insn (gen_mulsidi3 (tmp1, gen_lowpart (SImode, operands[1]), emit_insn (gen_mulsidi3 (tmp1, gen_lowpart (SImode, operands[1]),
gen_lowpart (SImode, operands[2]))); gen_lowpart (SImode, operands[2])));
emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (15))); emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (15)));
...@@ -181,13 +181,13 @@ ...@@ -181,13 +181,13 @@
rtx tmp1 = gen_reg_rtx (DImode); rtx tmp1 = gen_reg_rtx (DImode);
rtx tmp2 = gen_reg_rtx (SImode); rtx tmp2 = gen_reg_rtx (SImode);
rtx tmp3 = gen_reg_rtx (SImode); rtx tmp3 = gen_reg_rtx (SImode);
emit_insn (gen_umulsidi3 (tmp1, gen_lowpart (SImode, operands[1]), emit_insn (gen_umulsidi3 (tmp1, gen_lowpart (SImode, operands[1]),
gen_lowpart (SImode, operands[2]))); gen_lowpart (SImode, operands[2])));
emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (16))); emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (16)));
emit_insn (gen_ashlsi3 (tmp3, gen_highpart (SImode, tmp1), GEN_INT (16))); emit_insn (gen_ashlsi3 (tmp3, gen_highpart (SImode, tmp1), GEN_INT (16)));
emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3)); emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3));
DONE; DONE;
}) })
...@@ -217,7 +217,7 @@ ...@@ -217,7 +217,7 @@
} }
/* We have: /* We have:
31 high word 0 31 low word 0 31 high word 0 31 low word 0
[ S i i .... i i i ] [ i f f f ... f f ] [ S i i .... i i i ] [ i f f f ... f f ]
| |
...@@ -229,9 +229,18 @@ ...@@ -229,9 +229,18 @@
output_asm_insn ("ssat\\t%R3, #15, %R3", operands); output_asm_insn ("ssat\\t%R3, #15, %R3", operands);
output_asm_insn ("mrs\\t%4, APSR", operands); output_asm_insn ("mrs\\t%4, APSR", operands);
output_asm_insn ("tst\\t%4, #1<<27", operands); output_asm_insn ("tst\\t%4, #1<<27", operands);
if (TARGET_THUMB2) if (arm_restrict_it)
output_asm_insn ("it\\tne", operands); {
output_asm_insn ("mvnne\\t%Q3, %R3, asr #32", operands); output_asm_insn ("mvn\\t%4, %R3, asr #32", operands);
output_asm_insn ("it\\tne", operands);
output_asm_insn ("movne\\t%Q3, %4", operands);
}
else
{
if (TARGET_THUMB2)
output_asm_insn ("it\\tne", operands);
output_asm_insn ("mvnne\\t%Q3, %R3, asr #32", operands);
}
output_asm_insn ("mov\\t%0, %Q3, lsr #15", operands); output_asm_insn ("mov\\t%0, %Q3, lsr #15", operands);
output_asm_insn ("orr\\t%0, %0, %R3, asl #17", operands); output_asm_insn ("orr\\t%0, %0, %R3, asl #17", operands);
return ""; return "";
...@@ -239,7 +248,9 @@ ...@@ -239,7 +248,9 @@
[(set_attr "conds" "clob") [(set_attr "conds" "clob")
(set (attr "length") (set (attr "length")
(if_then_else (eq_attr "is_thumb" "yes") (if_then_else (eq_attr "is_thumb" "yes")
(const_int 38) (if_then_else (match_test "arm_restrict_it")
(const_int 40)
(const_int 38))
(const_int 32)))]) (const_int 32)))])
;; Same goes for this. ;; Same goes for this.
...@@ -265,7 +276,7 @@ ...@@ -265,7 +276,7 @@
} }
/* We have: /* We have:
31 high word 0 31 low word 0 31 high word 0 31 low word 0
[ i i i .... i i i ] [ f f f f ... f f ] [ i i i .... i i i ] [ f f f f ... f f ]
| |
...@@ -277,9 +288,18 @@ ...@@ -277,9 +288,18 @@
output_asm_insn ("usat\\t%R3, #16, %R3", operands); output_asm_insn ("usat\\t%R3, #16, %R3", operands);
output_asm_insn ("mrs\\t%4, APSR", operands); output_asm_insn ("mrs\\t%4, APSR", operands);
output_asm_insn ("tst\\t%4, #1<<27", operands); output_asm_insn ("tst\\t%4, #1<<27", operands);
if (TARGET_THUMB2) if (arm_restrict_it)
output_asm_insn ("it\\tne", operands); {
output_asm_insn ("sbfxne\\t%Q3, %R3, #15, #1", operands); output_asm_insn ("sbfx\\t%4, %R3, #15, #1", operands);
output_asm_insn ("it\\tne", operands);
output_asm_insn ("movne\\t%Q3, %4", operands);
}
else
{
if (TARGET_THUMB2)
output_asm_insn ("it\\tne", operands);
output_asm_insn ("sbfxne\\t%Q3, %R3, #15, #1", operands);
}
output_asm_insn ("lsr\\t%0, %Q3, #16", operands); output_asm_insn ("lsr\\t%0, %Q3, #16", operands);
output_asm_insn ("orr\\t%0, %0, %R3, asl #16", operands); output_asm_insn ("orr\\t%0, %0, %R3, asl #16", operands);
return ""; return "";
...@@ -287,7 +307,9 @@ ...@@ -287,7 +307,9 @@
[(set_attr "conds" "clob") [(set_attr "conds" "clob")
(set (attr "length") (set (attr "length")
(if_then_else (eq_attr "is_thumb" "yes") (if_then_else (eq_attr "is_thumb" "yes")
(const_int 38) (if_then_else (match_test "arm_restrict_it")
(const_int 40)
(const_int 38))
(const_int 32)))]) (const_int 32)))])
(define_expand "mulha3" (define_expand "mulha3"
...@@ -297,7 +319,7 @@ ...@@ -297,7 +319,7 @@
"TARGET_DSP_MULTIPLY && arm_arch_thumb2" "TARGET_DSP_MULTIPLY && arm_arch_thumb2"
{ {
rtx tmp = gen_reg_rtx (SImode); rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]), emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]),
gen_lowpart (HImode, operands[2]))); gen_lowpart (HImode, operands[2])));
emit_insn (gen_extv (gen_lowpart (SImode, operands[0]), tmp, GEN_INT (16), emit_insn (gen_extv (gen_lowpart (SImode, operands[0]), tmp, GEN_INT (16),
...@@ -315,7 +337,7 @@ ...@@ -315,7 +337,7 @@
rtx tmp1 = gen_reg_rtx (SImode); rtx tmp1 = gen_reg_rtx (SImode);
rtx tmp2 = gen_reg_rtx (SImode); rtx tmp2 = gen_reg_rtx (SImode);
rtx tmp3 = gen_reg_rtx (SImode); rtx tmp3 = gen_reg_rtx (SImode);
/* 8.8 * 8.8 -> 16.16 multiply. */ /* 8.8 * 8.8 -> 16.16 multiply. */
emit_insn (gen_zero_extendhisi2 (tmp1, gen_lowpart (HImode, operands[1]))); emit_insn (gen_zero_extendhisi2 (tmp1, gen_lowpart (HImode, operands[1])));
emit_insn (gen_zero_extendhisi2 (tmp2, gen_lowpart (HImode, operands[2]))); emit_insn (gen_zero_extendhisi2 (tmp2, gen_lowpart (HImode, operands[2])));
...@@ -334,7 +356,7 @@ ...@@ -334,7 +356,7 @@
{ {
rtx tmp = gen_reg_rtx (SImode); rtx tmp = gen_reg_rtx (SImode);
rtx rshift; rtx rshift;
emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]), emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]),
gen_lowpart (HImode, operands[2]))); gen_lowpart (HImode, operands[2])));
...@@ -356,12 +378,12 @@ ...@@ -356,12 +378,12 @@
rtx tmp2 = gen_reg_rtx (SImode); rtx tmp2 = gen_reg_rtx (SImode);
rtx tmp3 = gen_reg_rtx (SImode); rtx tmp3 = gen_reg_rtx (SImode);
rtx rshift_tmp = gen_reg_rtx (SImode); rtx rshift_tmp = gen_reg_rtx (SImode);
/* Note: there's no smul[bt][bt] equivalent for unsigned multiplies. Use a /* Note: there's no smul[bt][bt] equivalent for unsigned multiplies. Use a
normal 32x32->32-bit multiply instead. */ normal 32x32->32-bit multiply instead. */
emit_insn (gen_zero_extendhisi2 (tmp1, gen_lowpart (HImode, operands[1]))); emit_insn (gen_zero_extendhisi2 (tmp1, gen_lowpart (HImode, operands[1])));
emit_insn (gen_zero_extendhisi2 (tmp2, gen_lowpart (HImode, operands[2]))); emit_insn (gen_zero_extendhisi2 (tmp2, gen_lowpart (HImode, operands[2])));
emit_insn (gen_mulsi3 (tmp3, tmp1, tmp2)); emit_insn (gen_mulsi3 (tmp3, tmp1, tmp2));
/* The operand to "usat" is signed, so we cannot use the "..., asr #8" /* The operand to "usat" is signed, so we cannot use the "..., asr #8"
......
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