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Commit 1d61feeb by Terry Guo Committed by Xuepeng Guo
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types.md (alu_reg): Replaced by alu_sreg and alu_dsp_reg. 

2014-07-17  Terry Guo  <terry.guo@arm.com>

	* config/arm/types.md (alu_reg): Replaced by alu_sreg and alu_dsp_reg.
	(alus_reg): Renamed to alus_sreg.
	* config/arm/arm-fixed.md: Change type of non-dsp instructions
	from alu_reg to alu_sreg.  Change type of dsp instructions from
	alu_reg to alu_dsp_reg.
	* config/arm/thumb1.md: Likewise.
	* config/arm/thumb2.md: Likewise.
	* config/arm/arm.c (cortexa7_older_only): Use new ALU type names.
	* config/arm/arm1020e.md (1020alu_op): Replace alu_reg and alus_reg
	with alu_sreg and alus_sreg.
	* config/arm/arm1026ejs.md (alu_op): Likewise.
	* config/arm/arm1136jfs.md (11_alu_op): Likewise.
	* config/arm/arm926ejs.md (9_alu_op): Likewise.
	* config/arm/fa526.md (526_alu_op): Likewise.
	* config/arm/fa606te.md (606te_alu_op): Likewise.
	* config/arm/fa626te.md (626te_alu_op): Likewise.
	* config/arm/fa726te.md (726te_alu_op): Likewise.
	* config/arm/fmp626.md (mp626_alu_op): Likewise.
	* config/arm/arm.md (core_cycles): Replace alu_reg and alus_reg with
	alu_sreg, alu_dsp_reg and alus_sreg.     
	* config/arm/cortex-a15.md (cortex_a15_alu): Likewise.
	* config/arm/cortex-a5.md (cortex_a5_alu): Likewise.
	* config/arm/cortex-a53.md (cortex_a53_alu): Likewise.
	* config/arm/cortex-a7.md (cortex_a7_alu_sreg): Likewise.
	* config/arm/cortex-a8.md (cortex_a8_alu): Likewise.
	* config/arm/cortex-a9.md (cortex_a9_dp): Likewise.
	* config/arm/cortex-m4.md (cortex_m4_alu): Likewise.
	* config/arm/cortex-r4.md (cortex_r4_alu): Likewise.
	* config/arm/marvell-pj4.md (pj4_alu, pj4_alu_conds): Likewise.
	* config/aarch64/aarch64.md (*addsi3_aarch64, *addsi3_aarch64_uxtw,
	subsi3, *adddi3_aarch64, *subsi3_uxtw, subdi3, absdi2, neg<mode>2,
	*negsi2_uxtw, tlsle_small_<mode>): Rename type alu_reg to alu_sreg.     
	(add<mode>3_compare0, *addsi3_compare0_uxtw, *add<mode>3nr_compare0,
	sub<mode>3_compare0, *compare_neg<mode>, *neg<mode>2_compare0,
	subsi3_compare0_uxtw, *negsi2_compare0_uxtw, *cmp<mode>): Rename type 
	alus_reg to alus_sreg.

From-SVN: r212750
parent 72b9a00b
Showing with 141 additions and 98 deletions
gcc/ChangeLog
2014-07-17 Terry Guo <terry.guo@arm.com>
* config/arm/types.md (alu_reg): Replaced by alu_sreg and alu_dsp_reg.
(alus_reg): Renamed to alus_sreg.
* config/arm/arm-fixed.md: Change type of non-dsp instructions
from alu_reg to alu_sreg. Change type of dsp instructions from
alu_reg to alu_dsp_reg.
* config/arm/thumb1.md: Likewise.
* config/arm/thumb2.md: Likewise.
* config/arm/arm.c (cortexa7_older_only): Use new ALU type names.
* config/arm/arm1020e.md (1020alu_op): Replace alu_reg and alus_reg
with alu_sreg and alus_sreg.
* config/arm/arm1026ejs.md (alu_op): Likewise.
* config/arm/arm1136jfs.md (11_alu_op): Likewise.
* config/arm/arm926ejs.md (9_alu_op): Likewise.
* config/arm/fa526.md (526_alu_op): Likewise.
* config/arm/fa606te.md (606te_alu_op): Likewise.
* config/arm/fa626te.md (626te_alu_op): Likewise.
* config/arm/fa726te.md (726te_alu_op): Likewise.
* config/arm/fmp626.md (mp626_alu_op): Likewise.
* config/arm/arm.md (core_cycles): Replace alu_reg and alus_reg with
alu_sreg, alu_dsp_reg and alus_sreg.
* config/arm/cortex-a15.md (cortex_a15_alu): Likewise.
* config/arm/cortex-a5.md (cortex_a5_alu): Likewise.
* config/arm/cortex-a53.md (cortex_a53_alu): Likewise.
* config/arm/cortex-a7.md (cortex_a7_alu_sreg): Likewise.
* config/arm/cortex-a8.md (cortex_a8_alu): Likewise.
* config/arm/cortex-a9.md (cortex_a9_dp): Likewise.
* config/arm/cortex-m4.md (cortex_m4_alu): Likewise.
* config/arm/cortex-r4.md (cortex_r4_alu): Likewise.
* config/arm/marvell-pj4.md (pj4_alu, pj4_alu_conds): Likewise.
* config/aarch64/aarch64.md (*addsi3_aarch64, *addsi3_aarch64_uxtw,
subsi3, *adddi3_aarch64, *subsi3_uxtw, subdi3, absdi2, neg<mode>2,
*negsi2_uxtw, tlsle_small_<mode>): Rename type alu_reg to alu_sreg.
(add<mode>3_compare0, *addsi3_compare0_uxtw, *add<mode>3nr_compare0,
sub<mode>3_compare0, *compare_neg<mode>, *neg<mode>2_compare0,
subsi3_compare0_uxtw, *negsi2_compare0_uxtw, *cmp<mode>): Rename type
alus_reg to alus_sreg.
2014-07-17 Andreas Schwab <schwab@linux-m68k.org> 2014-07-17 Andreas Schwab <schwab@linux-m68k.org>
* real.c (encode_ieee_extended_motorola): Clear integer bit in the * real.c (encode_ieee_extended_motorola): Clear integer bit in the
......
gcc/config/aarch64/aarch64.md
...@@ -1167,7 +1167,7 @@ ...@@ -1167,7 +1167,7 @@
add\\t%w0, %w1, %w2 add\\t%w0, %w1, %w2
add\\t%0.2s, %1.2s, %2.2s add\\t%0.2s, %1.2s, %2.2s
sub\\t%w0, %w1, #%n2" sub\\t%w0, %w1, #%n2"
[(set_attr "type" "alu_imm,alu_reg,neon_add,alu_imm") [(set_attr "type" "alu_imm,alu_sreg,neon_add,alu_imm")
(set_attr "simd" "*,*,yes,*")] (set_attr "simd" "*,*,yes,*")]
) )
...@@ -1183,7 +1183,7 @@ ...@@ -1183,7 +1183,7 @@
add\\t%w0, %w1, %2 add\\t%w0, %w1, %2
add\\t%w0, %w1, %w2 add\\t%w0, %w1, %w2
sub\\t%w0, %w1, #%n2" sub\\t%w0, %w1, #%n2"
[(set_attr "type" "alu_imm,alu_reg,alu_imm")] [(set_attr "type" "alu_imm,alu_sreg,alu_imm")]
) )
(define_insn "*adddi3_aarch64" (define_insn "*adddi3_aarch64"
...@@ -1198,7 +1198,7 @@ ...@@ -1198,7 +1198,7 @@
add\\t%x0, %x1, %x2 add\\t%x0, %x1, %x2
sub\\t%x0, %x1, #%n2 sub\\t%x0, %x1, #%n2
add\\t%d0, %d1, %d2" add\\t%d0, %d1, %d2"
[(set_attr "type" "alu_imm,alu_reg,alu_imm,alu_reg") [(set_attr "type" "alu_imm,alu_sreg,alu_imm,alu_sreg")
(set_attr "simd" "*,*,*,yes")] (set_attr "simd" "*,*,*,yes")]
) )
...@@ -1234,7 +1234,7 @@ ...@@ -1234,7 +1234,7 @@
adds\\t%<w>0, %<w>1, %<w>2 adds\\t%<w>0, %<w>1, %<w>2
adds\\t%<w>0, %<w>1, %<w>2 adds\\t%<w>0, %<w>1, %<w>2
subs\\t%<w>0, %<w>1, #%n2" subs\\t%<w>0, %<w>1, #%n2"
[(set_attr "type" "alus_reg,alus_imm,alus_imm")] [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
) )
;; zero_extend version of above ;; zero_extend version of above
...@@ -1251,7 +1251,7 @@ ...@@ -1251,7 +1251,7 @@
adds\\t%w0, %w1, %w2 adds\\t%w0, %w1, %w2
adds\\t%w0, %w1, %w2 adds\\t%w0, %w1, %w2
subs\\t%w0, %w1, #%n2" subs\\t%w0, %w1, #%n2"
[(set_attr "type" "alus_reg,alus_imm,alus_imm")] [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
) )
(define_insn "*adds_mul_imm_<mode>" (define_insn "*adds_mul_imm_<mode>"
...@@ -1365,7 +1365,7 @@ ...@@ -1365,7 +1365,7 @@
cmn\\t%<w>0, %<w>1 cmn\\t%<w>0, %<w>1
cmn\\t%<w>0, %<w>1 cmn\\t%<w>0, %<w>1
cmp\\t%<w>0, #%n1" cmp\\t%<w>0, #%n1"
[(set_attr "type" "alus_reg,alus_imm,alus_imm")] [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
) )
(define_insn "*compare_neg<mode>" (define_insn "*compare_neg<mode>"
...@@ -1375,7 +1375,7 @@ ...@@ -1375,7 +1375,7 @@
(match_operand:GPI 1 "register_operand" "r")))] (match_operand:GPI 1 "register_operand" "r")))]
"" ""
"cmn\\t%<w>1, %<w>0" "cmn\\t%<w>1, %<w>0"
[(set_attr "type" "alus_reg")] [(set_attr "type" "alus_sreg")]
) )
(define_insn "*add_<shift>_<mode>" (define_insn "*add_<shift>_<mode>"
...@@ -1647,7 +1647,7 @@ ...@@ -1647,7 +1647,7 @@
(match_operand:SI 2 "register_operand" "r")))] (match_operand:SI 2 "register_operand" "r")))]
"" ""
"sub\\t%w0, %w1, %w2" "sub\\t%w0, %w1, %w2"
[(set_attr "type" "alu_reg")] [(set_attr "type" "alu_sreg")]
) )
;; zero_extend version of above ;; zero_extend version of above
...@@ -1658,7 +1658,7 @@ ...@@ -1658,7 +1658,7 @@
(match_operand:SI 2 "register_operand" "r"))))] (match_operand:SI 2 "register_operand" "r"))))]
"" ""
"sub\\t%w0, %w1, %w2" "sub\\t%w0, %w1, %w2"
[(set_attr "type" "alu_reg")] [(set_attr "type" "alu_sreg")]
) )
(define_insn "subdi3" (define_insn "subdi3"
...@@ -1669,7 +1669,7 @@ ...@@ -1669,7 +1669,7 @@
"@ "@
sub\\t%x0, %x1, %x2 sub\\t%x0, %x1, %x2
sub\\t%d0, %d1, %d2" sub\\t%d0, %d1, %d2"
[(set_attr "type" "alu_reg, neon_sub") [(set_attr "type" "alu_sreg, neon_sub")
(set_attr "simd" "*,yes")] (set_attr "simd" "*,yes")]
) )
...@@ -1701,7 +1701,7 @@ ...@@ -1701,7 +1701,7 @@
(minus:GPI (match_dup 1) (match_dup 2)))] (minus:GPI (match_dup 1) (match_dup 2)))]
"" ""
"subs\\t%<w>0, %<w>1, %<w>2" "subs\\t%<w>0, %<w>1, %<w>2"
[(set_attr "type" "alus_reg")] [(set_attr "type" "alus_sreg")]
) )
;; zero_extend version of above ;; zero_extend version of above
...@@ -1714,7 +1714,7 @@ ...@@ -1714,7 +1714,7 @@
(zero_extend:DI (minus:SI (match_dup 1) (match_dup 2))))] (zero_extend:DI (minus:SI (match_dup 1) (match_dup 2))))]
"" ""
"subs\\t%w0, %w1, %w2" "subs\\t%w0, %w1, %w2"
[(set_attr "type" "alus_reg")] [(set_attr "type" "alus_sreg")]
) )
(define_insn "*sub_<shift>_<mode>" (define_insn "*sub_<shift>_<mode>"
...@@ -1925,7 +1925,7 @@ ...@@ -1925,7 +1925,7 @@
GEN_INT (63))))); GEN_INT (63)))));
DONE; DONE;
} }
[(set_attr "type" "alu_reg")] [(set_attr "type" "alu_sreg")]
) )
(define_insn "neg<mode>2" (define_insn "neg<mode>2"
...@@ -1935,7 +1935,7 @@ ...@@ -1935,7 +1935,7 @@
"@ "@
neg\\t%<w>0, %<w>1 neg\\t%<w>0, %<w>1
neg\\t%<rtn>0<vas>, %<rtn>1<vas>" neg\\t%<rtn>0<vas>, %<rtn>1<vas>"
[(set_attr "type" "alu_reg, neon_neg<q>") [(set_attr "type" "alu_sreg, neon_neg<q>")
(set_attr "simd" "*,yes")] (set_attr "simd" "*,yes")]
) )
...@@ -1945,7 +1945,7 @@ ...@@ -1945,7 +1945,7 @@
(zero_extend:DI (neg:SI (match_operand:SI 1 "register_operand" "r"))))] (zero_extend:DI (neg:SI (match_operand:SI 1 "register_operand" "r"))))]
"" ""
"neg\\t%w0, %w1" "neg\\t%w0, %w1"
[(set_attr "type" "alu_reg")] [(set_attr "type" "alu_sreg")]
) )
(define_insn "*ngc<mode>" (define_insn "*ngc<mode>"
...@@ -1975,7 +1975,7 @@ ...@@ -1975,7 +1975,7 @@
(neg:GPI (match_dup 1)))] (neg:GPI (match_dup 1)))]
"" ""
"negs\\t%<w>0, %<w>1" "negs\\t%<w>0, %<w>1"
[(set_attr "type" "alus_reg")] [(set_attr "type" "alus_sreg")]
) )
;; zero_extend version of above ;; zero_extend version of above
...@@ -1987,7 +1987,7 @@ ...@@ -1987,7 +1987,7 @@
(zero_extend:DI (neg:SI (match_dup 1))))] (zero_extend:DI (neg:SI (match_dup 1))))]
"" ""
"negs\\t%w0, %w1" "negs\\t%w0, %w1"
[(set_attr "type" "alus_reg")] [(set_attr "type" "alus_sreg")]
) )
(define_insn "*neg_<shift><mode>3_compare0" (define_insn "*neg_<shift><mode>3_compare0"
...@@ -2266,7 +2266,7 @@ ...@@ -2266,7 +2266,7 @@
cmp\\t%<w>0, %<w>1 cmp\\t%<w>0, %<w>1
cmp\\t%<w>0, %<w>1 cmp\\t%<w>0, %<w>1
cmn\\t%<w>0, #%n1" cmn\\t%<w>0, #%n1"
[(set_attr "type" "alus_reg,alus_imm,alus_imm")] [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
) )
(define_insn "*cmp<mode>" (define_insn "*cmp<mode>"
...@@ -3901,7 +3901,7 @@ ...@@ -3901,7 +3901,7 @@
UNSPEC_GOTSMALLTLS))] UNSPEC_GOTSMALLTLS))]
"" ""
"add\\t%<w>0, %<w>1, #%G2\;add\\t%<w>0, %<w>0, #%L2" "add\\t%<w>0, %<w>1, #%G2\;add\\t%<w>0, %<w>0, #%L2"
[(set_attr "type" "alu_reg") [(set_attr "type" "alu_sreg")
(set_attr "length" "8")] (set_attr "length" "8")]
) )
......
gcc/config/arm/arm-fixed.md
...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
"add%?\\t%0, %1, %2" "add%?\\t%0, %1, %2"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,no") (set_attr "predicable_short_it" "yes,no")
(set_attr "type" "alu_reg")]) (set_attr "type" "alu_sreg")])
(define_insn "add<mode>3" (define_insn "add<mode>3"
[(set (match_operand:ADDSUB 0 "s_register_operand" "=r") [(set (match_operand:ADDSUB 0 "s_register_operand" "=r")
...@@ -36,7 +36,7 @@ ...@@ -36,7 +36,7 @@
"sadd<qaddsub_suf>%?\\t%0, %1, %2" "sadd<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no") (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_reg")]) (set_attr "type" "alu_dsp_reg")])
(define_insn "usadd<mode>3" (define_insn "usadd<mode>3"
[(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r")
...@@ -46,7 +46,7 @@ ...@@ -46,7 +46,7 @@
"uqadd<qaddsub_suf>%?\\t%0, %1, %2" "uqadd<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no") (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_reg")]) (set_attr "type" "alu_dsp_reg")])
(define_insn "ssadd<mode>3" (define_insn "ssadd<mode>3"
[(set (match_operand:QADDSUB 0 "s_register_operand" "=r") [(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
...@@ -56,7 +56,7 @@ ...@@ -56,7 +56,7 @@
"qadd<qaddsub_suf>%?\\t%0, %1, %2" "qadd<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no") (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_reg")]) (set_attr "type" "alu_dsp_reg")])
(define_insn "sub<mode>3" (define_insn "sub<mode>3"
[(set (match_operand:FIXED 0 "s_register_operand" "=l,r") [(set (match_operand:FIXED 0 "s_register_operand" "=l,r")
...@@ -66,7 +66,7 @@ ...@@ -66,7 +66,7 @@
"sub%?\\t%0, %1, %2" "sub%?\\t%0, %1, %2"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,no") (set_attr "predicable_short_it" "yes,no")
(set_attr "type" "alu_reg")]) (set_attr "type" "alu_sreg")])
(define_insn "sub<mode>3" (define_insn "sub<mode>3"
[(set (match_operand:ADDSUB 0 "s_register_operand" "=r") [(set (match_operand:ADDSUB 0 "s_register_operand" "=r")
...@@ -76,7 +76,7 @@ ...@@ -76,7 +76,7 @@
"ssub<qaddsub_suf>%?\\t%0, %1, %2" "ssub<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no") (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_reg")]) (set_attr "type" "alu_dsp_reg")])
(define_insn "ussub<mode>3" (define_insn "ussub<mode>3"
[(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r")
...@@ -87,7 +87,7 @@ ...@@ -87,7 +87,7 @@
"uqsub<qaddsub_suf>%?\\t%0, %1, %2" "uqsub<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no") (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_reg")]) (set_attr "type" "alu_dsp_reg")])
(define_insn "sssub<mode>3" (define_insn "sssub<mode>3"
[(set (match_operand:QADDSUB 0 "s_register_operand" "=r") [(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
...@@ -97,7 +97,7 @@ ...@@ -97,7 +97,7 @@
"qsub<qaddsub_suf>%?\\t%0, %1, %2" "qsub<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no") (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_reg")]) (set_attr "type" "alu_dsp_reg")])
;; Fractional multiplies. ;; Fractional multiplies.
......
gcc/config/arm/arm.c
...@@ -11710,8 +11710,9 @@ cortexa7_older_only (rtx insn) ...@@ -11710,8 +11710,9 @@ cortexa7_older_only (rtx insn)
switch (get_attr_type (insn)) switch (get_attr_type (insn))
{ {
case TYPE_ALU_REG: case TYPE_ALU_DSP_REG:
case TYPE_ALUS_REG: case TYPE_ALU_SREG:
case TYPE_ALUS_SREG:
case TYPE_LOGIC_REG: case TYPE_LOGIC_REG:
case TYPE_LOGICS_REG: case TYPE_LOGICS_REG:
case TYPE_ADC_REG: case TYPE_ADC_REG:
......
gcc/config/arm/arm.md
...@@ -320,8 +320,8 @@ ...@@ -320,8 +320,8 @@
; than one on the main cpu execution unit. ; than one on the main cpu execution unit.
(define_attr "core_cycles" "single,multi" (define_attr "core_cycles" "single,multi"
(if_then_else (eq_attr "type" (if_then_else (eq_attr "type"
"adc_imm, adc_reg, adcs_imm, adcs_reg, adr, alu_ext, alu_imm, alu_reg,\ "adc_imm, adc_reg, adcs_imm, adcs_reg, adr, alu_ext, alu_imm, alu_sreg,\
alu_shift_imm, alu_shift_reg, alus_ext, alus_imm, alus_reg,\ alu_shift_imm, alu_shift_reg, alu_dsp_reg, alus_ext, alus_imm, alus_sreg,\
alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\ alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\
logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\ logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\
logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\ logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\
...@@ -602,7 +602,7 @@ ...@@ -602,7 +602,7 @@
(set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*") (set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
(const_string "alu_imm") (const_string "alu_imm")
(const_string "alu_reg"))) (const_string "alu_sreg")))
] ]
) )
...@@ -620,7 +620,7 @@ ...@@ -620,7 +620,7 @@
sub%.\\t%0, %1, #%n2 sub%.\\t%0, %1, #%n2
add%.\\t%0, %1, %2" add%.\\t%0, %1, %2"
[(set_attr "conds" "set") [(set_attr "conds" "set")
(set_attr "type" "alus_imm,alus_imm,alus_reg")] (set_attr "type" "alus_imm,alus_imm,alus_sreg")]
) )
(define_insn "*addsi3_compare0_scratch" (define_insn "*addsi3_compare0_scratch"
...@@ -636,7 +636,7 @@ ...@@ -636,7 +636,7 @@
cmn%?\\t%0, %1" cmn%?\\t%0, %1"
[(set_attr "conds" "set") [(set_attr "conds" "set")
(set_attr "predicable" "yes") (set_attr "predicable" "yes")
(set_attr "type" "alus_imm,alus_imm,alus_reg")] (set_attr "type" "alus_imm,alus_imm,alus_sreg")]
) )
(define_insn "*compare_negsi_si" (define_insn "*compare_negsi_si"
...@@ -651,7 +651,7 @@ ...@@ -651,7 +651,7 @@
(set_attr "arch" "t2,*") (set_attr "arch" "t2,*")
(set_attr "length" "2,4") (set_attr "length" "2,4")
(set_attr "predicable_short_it" "yes,no") (set_attr "predicable_short_it" "yes,no")
(set_attr "type" "alus_reg")] (set_attr "type" "alus_sreg")]
) )
;; This is the canonicalization of addsi3_compare0_for_combiner when the ;; This is the canonicalization of addsi3_compare0_for_combiner when the
...@@ -669,7 +669,7 @@ ...@@ -669,7 +669,7 @@
add%.\\t%0, %1, %3 add%.\\t%0, %1, %3
sub%.\\t%0, %1, #%n3" sub%.\\t%0, %1, #%n3"
[(set_attr "conds" "set") [(set_attr "conds" "set")
(set_attr "type" "alus_reg")] (set_attr "type" "alus_sreg")]
) )
;; Convert the sequence ;; Convert the sequence
...@@ -727,7 +727,7 @@ ...@@ -727,7 +727,7 @@
sub%.\\t%0, %1, #%n2 sub%.\\t%0, %1, #%n2
add%.\\t%0, %1, %2" add%.\\t%0, %1, %2"
[(set_attr "conds" "set") [(set_attr "conds" "set")
(set_attr "type" "alus_imm,alus_imm,alus_reg")] (set_attr "type" "alus_imm,alus_imm,alus_sreg")]
) )
(define_insn "*addsi3_compare_op2" (define_insn "*addsi3_compare_op2"
...@@ -744,7 +744,7 @@ ...@@ -744,7 +744,7 @@
add%.\\t%0, %1, %2 add%.\\t%0, %1, %2
sub%.\\t%0, %1, #%n2" sub%.\\t%0, %1, #%n2"
[(set_attr "conds" "set") [(set_attr "conds" "set")
(set_attr "type" "alus_imm,alus_imm,alus_reg")] (set_attr "type" "alus_imm,alus_imm,alus_sreg")]
) )
(define_insn "*compare_addsi2_op0" (define_insn "*compare_addsi2_op0"
...@@ -765,7 +765,7 @@ ...@@ -765,7 +765,7 @@
(set_attr "arch" "t2,t2,*,*,*") (set_attr "arch" "t2,t2,*,*,*")
(set_attr "predicable_short_it" "yes,yes,no,no,no") (set_attr "predicable_short_it" "yes,yes,no,no,no")
(set_attr "length" "2,2,4,4,4") (set_attr "length" "2,2,4,4,4")
(set_attr "type" "alus_imm,alus_reg,alus_imm,alus_imm,alus_reg")] (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_imm,alus_sreg")]
) )
(define_insn "*compare_addsi2_op1" (define_insn "*compare_addsi2_op1"
...@@ -786,7 +786,7 @@ ...@@ -786,7 +786,7 @@
(set_attr "arch" "t2,t2,*,*,*") (set_attr "arch" "t2,t2,*,*,*")
(set_attr "predicable_short_it" "yes,yes,no,no,no") (set_attr "predicable_short_it" "yes,yes,no,no,no")
(set_attr "length" "2,2,4,4,4") (set_attr "length" "2,2,4,4,4")
(set_attr "type" "alus_imm,alus_reg,alus_imm,alus_imm,alus_reg")] (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_imm,alus_sreg")]
) )
(define_insn "*addsi3_carryin_<optab>" (define_insn "*addsi3_carryin_<optab>"
...@@ -1201,7 +1201,7 @@ ...@@ -1201,7 +1201,7 @@
(set_attr "arch" "t2,t2,t2,t2,*,*,*,*,*") (set_attr "arch" "t2,t2,t2,t2,*,*,*,*,*")
(set_attr "predicable" "yes") (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no") (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no")
(set_attr "type" "alu_reg,alu_reg,alu_reg,alu_reg,alu_imm,alu_imm,alu_reg,alu_reg,multiple")] (set_attr "type" "alu_sreg,alu_sreg,alu_sreg,alu_sreg,alu_imm,alu_imm,alu_sreg,alu_sreg,multiple")]
) )
(define_peephole2 (define_peephole2
...@@ -1231,7 +1231,7 @@ ...@@ -1231,7 +1231,7 @@
sub%.\\t%0, %1, %2 sub%.\\t%0, %1, %2
rsb%.\\t%0, %2, %1" rsb%.\\t%0, %2, %1"
[(set_attr "conds" "set") [(set_attr "conds" "set")
(set_attr "type" "alus_imm,alus_reg,alus_reg")] (set_attr "type" "alus_imm,alus_sreg,alus_sreg")]
) )
(define_insn "subsi3_compare" (define_insn "subsi3_compare"
...@@ -1246,7 +1246,7 @@ ...@@ -1246,7 +1246,7 @@
sub%.\\t%0, %1, %2 sub%.\\t%0, %1, %2
rsb%.\\t%0, %2, %1" rsb%.\\t%0, %2, %1"
[(set_attr "conds" "set") [(set_attr "conds" "set")
(set_attr "type" "alus_imm,alus_reg,alus_reg")] (set_attr "type" "alus_imm,alus_sreg,alus_sreg")]
) )
(define_expand "subsf3" (define_expand "subsf3"
...@@ -4366,7 +4366,7 @@ ...@@ -4366,7 +4366,7 @@
(set_attr "predicable_short_it" "yes,no") (set_attr "predicable_short_it" "yes,no")
(set_attr "arch" "t2,*") (set_attr "arch" "t2,*")
(set_attr "length" "4") (set_attr "length" "4")
(set_attr "type" "alu_reg")] (set_attr "type" "alu_sreg")]
) )
(define_expand "negsf2" (define_expand "negsf2"
...@@ -5828,7 +5828,7 @@ ...@@ -5828,7 +5828,7 @@
return \"add\\t%0, %|pc\"; return \"add\\t%0, %|pc\";
" "
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "type" "alu_reg")] (set_attr "type" "alu_sreg")]
) )
(define_insn "pic_add_dot_plus_eight" (define_insn "pic_add_dot_plus_eight"
...@@ -5844,7 +5844,7 @@ ...@@ -5844,7 +5844,7 @@
return \"add%?\\t%0, %|pc, %1\"; return \"add%?\\t%0, %|pc, %1\";
" "
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "type" "alu_reg")] (set_attr "type" "alu_sreg")]
) )
(define_insn "tls_load_dot_plus_eight" (define_insn "tls_load_dot_plus_eight"
...@@ -6857,7 +6857,7 @@ ...@@ -6857,7 +6857,7 @@
(set_attr "length" "2,2,4,4,4") (set_attr "length" "2,2,4,4,4")
(set_attr "predicable" "yes") (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,yes,yes,no,no") (set_attr "predicable_short_it" "yes,yes,yes,no,no")
(set_attr "type" "alus_imm,alus_reg,alus_reg,alus_imm,alus_imm")] (set_attr "type" "alus_imm,alus_sreg,alus_sreg,alus_imm,alus_imm")]
) )
(define_insn "*cmpsi_shiftsi" (define_insn "*cmpsi_shiftsi"
...@@ -9430,10 +9430,10 @@ ...@@ -9430,10 +9430,10 @@
(set_attr_alternative "type" (set_attr_alternative "type"
[(if_then_else (match_operand 3 "const_int_operand" "") [(if_then_else (match_operand 3 "const_int_operand" "")
(const_string "alu_imm" ) (const_string "alu_imm" )
(const_string "alu_reg")) (const_string "alu_sreg"))
(const_string "alu_imm") (const_string "alu_imm")
(const_string "alu_reg") (const_string "alu_sreg")
(const_string "alu_reg")])] (const_string "alu_sreg")])]
) )
(define_insn "*ifcompare_move_plus" (define_insn "*ifcompare_move_plus"
...@@ -9470,7 +9470,7 @@ ...@@ -9470,7 +9470,7 @@
sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1" sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1"
[(set_attr "conds" "use") [(set_attr "conds" "use")
(set_attr "length" "4,4,8,8") (set_attr "length" "4,4,8,8")
(set_attr "type" "alu_reg,alu_imm,multiple,multiple")] (set_attr "type" "alu_sreg,alu_imm,multiple,multiple")]
) )
(define_insn "*ifcompare_arith_arith" (define_insn "*ifcompare_arith_arith"
......
gcc/config/arm/arm1020e.md
...@@ -67,7 +67,7 @@ ...@@ -67,7 +67,7 @@
(define_insn_reservation "1020alu_op" 1 (define_insn_reservation "1020alu_op" 1
(and (eq_attr "tune" "arm1020e,arm1022e") (and (eq_attr "tune" "arm1020e,arm1022e")
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\ adr,bfm,rev,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
......
gcc/config/arm/arm1026ejs.md
...@@ -67,7 +67,7 @@ ...@@ -67,7 +67,7 @@
(define_insn_reservation "alu_op" 1 (define_insn_reservation "alu_op" 1
(and (eq_attr "tune" "arm1026ejs") (and (eq_attr "tune" "arm1026ejs")
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\ adr,bfm,rev,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
......
gcc/config/arm/arm1136jfs.md
...@@ -76,7 +76,7 @@ ...@@ -76,7 +76,7 @@
(define_insn_reservation "11_alu_op" 2 (define_insn_reservation "11_alu_op" 2
(and (eq_attr "tune" "arm1136js,arm1136jfs") (and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\ adr,bfm,rev,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
......
gcc/config/arm/arm926ejs.md
...@@ -59,7 +59,7 @@ ...@@ -59,7 +59,7 @@
(define_insn_reservation "9_alu_op" 1 (define_insn_reservation "9_alu_op" 1
(and (eq_attr "tune" "arm926ejs") (and (eq_attr "tune" "arm926ejs")
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\ adr,bfm,rev,\
alu_shift_imm,alus_shift_imm,\ alu_shift_imm,alus_shift_imm,\
......
gcc/config/arm/cortex-a15.md
...@@ -62,9 +62,9 @@ ...@@ -62,9 +62,9 @@
(define_insn_reservation "cortex_a15_alu" 2 (define_insn_reservation "cortex_a15_alu" 2
(and (eq_attr "tune" "cortexa15") (and (eq_attr "tune" "cortexa15")
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,clz,rbit,rev,\ adr,bfm,clz,rbit,rev,alu_dsp_reg,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
mov_imm,mov_reg,\ mov_imm,mov_reg,\
mvn_imm,mvn_reg,\ mvn_imm,mvn_reg,\
......
gcc/config/arm/cortex-a5.md
...@@ -59,9 +59,9 @@ ...@@ -59,9 +59,9 @@
(define_insn_reservation "cortex_a5_alu" 2 (define_insn_reservation "cortex_a5_alu" 2
(and (eq_attr "tune" "cortexa5") (and (eq_attr "tune" "cortexa5")
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,clz,rbit,rev,\ adr,bfm,clz,rbit,rev,alu_dsp_reg,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\
mrs,multiple,no_insn")) mrs,multiple,no_insn"))
......
gcc/config/arm/cortex-a53.md
...@@ -73,9 +73,9 @@ ...@@ -73,9 +73,9 @@
(define_insn_reservation "cortex_a53_alu" 2 (define_insn_reservation "cortex_a53_alu" 2
(and (eq_attr "tune" "cortexa53") (and (eq_attr "tune" "cortexa53")
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,csel,clz,rbit,rev,\ adr,bfm,csel,clz,rbit,rev,alu_dsp_reg,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\
mrs,multiple,no_insn")) mrs,multiple,no_insn"))
......
gcc/config/arm/cortex-a7.md
...@@ -133,11 +133,11 @@ ...@@ -133,11 +133,11 @@
;; ALU instruction with register operands can dual-issue ;; ALU instruction with register operands can dual-issue
;; with a younger immediate-based instruction. ;; with a younger immediate-based instruction.
(define_insn_reservation "cortex_a7_alu_reg" 2 (define_insn_reservation "cortex_a7_alu_sreg" 2
(and (eq_attr "tune" "cortexa7") (and (eq_attr "tune" "cortexa7")
(eq_attr "type" "alu_reg,alus_reg,logic_reg,logics_reg,\ (eq_attr "type" "alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
bfm,clz,rbit,rev,\ bfm,clz,rbit,rev,alu_dsp_reg,\
shift_imm,shift_reg,mov_reg,mvn_reg")) shift_imm,shift_reg,mov_reg,mvn_reg"))
"cortex_a7_ex1") "cortex_a7_ex1")
...@@ -153,14 +153,14 @@ ...@@ -153,14 +153,14 @@
"cortex_a7_ex1") "cortex_a7_ex1")
;; Forwarding path for unshifted operands. ;; Forwarding path for unshifted operands.
(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift" (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_alu_shift"
"cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_mul") "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_mul")
(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift" (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_alu_shift"
"cortex_a7_store*" "cortex_a7_store*"
"arm_no_early_store_addr_dep") "arm_no_early_store_addr_dep")
(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift" (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_alu_shift"
"cortex_a7_alu_shift" "cortex_a7_alu_shift"
"arm_no_early_alu_shift_dep") "arm_no_early_alu_shift_dep")
......
gcc/config/arm/cortex-a8.md
...@@ -86,9 +86,9 @@ ...@@ -86,9 +86,9 @@
(define_insn_reservation "cortex_a8_alu" 2 (define_insn_reservation "cortex_a8_alu" 2
(and (eq_attr "tune" "cortexa8") (and (eq_attr "tune" "cortexa8")
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,clz,rbit,rev,\ adr,bfm,clz,rbit,rev,alu_dsp_reg,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
multiple,no_insn")) multiple,no_insn"))
"cortex_a8_default") "cortex_a8_default")
......
gcc/config/arm/cortex-a9.md
...@@ -81,9 +81,9 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1") ...@@ -81,9 +81,9 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
(define_insn_reservation "cortex_a9_dp" 2 (define_insn_reservation "cortex_a9_dp" 2
(and (eq_attr "tune" "cortexa9") (and (eq_attr "tune" "cortexa9")
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,clz,rbit,rev,\ adr,bfm,clz,rbit,rev,alu_dsp_reg,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\
mov_shift_reg,mov_shift,\ mov_shift_reg,mov_shift,\
......
gcc/config/arm/cortex-m4.md
...@@ -32,9 +32,9 @@ ...@@ -32,9 +32,9 @@
(define_insn_reservation "cortex_m4_alu" 1 (define_insn_reservation "cortex_m4_alu" 1
(and (eq_attr "tune" "cortexm4") (and (eq_attr "tune" "cortexm4")
(ior (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ (ior (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,clz,rbit,rev,\ adr,bfm,clz,rbit,rev,alu_dsp_reg,\
shift_imm,shift_reg,extend,\ shift_imm,shift_reg,extend,\
alu_shift_imm,alus_shift_imm,\ alu_shift_imm,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\ logic_shift_imm,logics_shift_imm,\
......
gcc/config/arm/cortex-r4.md
...@@ -79,7 +79,7 @@ ...@@ -79,7 +79,7 @@
(define_insn_reservation "cortex_r4_alu" 2 (define_insn_reservation "cortex_r4_alu" 2
(and (eq_attr "tune_cortexr4" "yes") (and (eq_attr "tune_cortexr4" "yes")
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,clz,rbit,rev,\ adr,bfm,clz,rbit,rev,\
shift_imm,shift_reg,mvn_imm,mvn_reg")) shift_imm,shift_reg,mvn_imm,mvn_reg"))
......
gcc/config/arm/fa526.md
...@@ -63,7 +63,7 @@ ...@@ -63,7 +63,7 @@
(define_insn_reservation "526_alu_op" 1 (define_insn_reservation "526_alu_op" 1
(and (eq_attr "tune" "fa526") (and (eq_attr "tune" "fa526")
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\ adr,bfm,rev,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
......
gcc/config/arm/fa606te.md
...@@ -63,7 +63,7 @@ ...@@ -63,7 +63,7 @@
(define_insn_reservation "606te_alu_op" 1 (define_insn_reservation "606te_alu_op" 1
(and (eq_attr "tune" "fa606te") (and (eq_attr "tune" "fa606te")
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\ adr,bfm,rev,\
shift_imm,shift_reg,extend,\ shift_imm,shift_reg,extend,\
......
gcc/config/arm/fa626te.md
...@@ -69,7 +69,7 @@ ...@@ -69,7 +69,7 @@
(define_insn_reservation "626te_alu_op" 1 (define_insn_reservation "626te_alu_op" 1
(and (eq_attr "tune" "fa626,fa626te") (and (eq_attr "tune" "fa626,fa626te")
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\ adr,bfm,rev,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
......
gcc/config/arm/fa726te.md
...@@ -87,7 +87,7 @@ ...@@ -87,7 +87,7 @@
(define_insn_reservation "726te_alu_op" 1 (define_insn_reservation "726te_alu_op" 1
(and (eq_attr "tune" "fa726te") (and (eq_attr "tune" "fa726te")
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_reg,alus_reg,logic_reg,logics_reg,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\ adr,bfm,rev,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
......
gcc/config/arm/fmp626.md
...@@ -63,7 +63,7 @@ ...@@ -63,7 +63,7 @@
;; ALU operations ;; ALU operations
(define_insn_reservation "mp626_alu_op" 1 (define_insn_reservation "mp626_alu_op" 1
(and (eq_attr "tune" "fmp626") (and (eq_attr "tune" "fmp626")
(eq_attr "type" "alu_imm,alus_imm,alu_reg,alus_reg,\ (eq_attr "type" "alu_imm,alus_imm,alu_sreg,alus_sreg,\
logic_imm,logics_imm,logic_reg,logics_reg,\ logic_imm,logics_imm,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\ adr,bfm,rev,\
......
gcc/config/arm/marvell-pj4.md
...@@ -53,20 +53,20 @@ ...@@ -53,20 +53,20 @@
(define_insn_reservation "pj4_alu" 1 (define_insn_reservation "pj4_alu" 1
(and (eq_attr "tune" "marvell_pj4") (and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "alu_imm,alus_imm,alu_reg,alus_reg,\ (eq_attr "type" "alu_imm,alus_imm,alu_sreg,alus_sreg,\
logic_imm,logics_imm,logic_reg,logics_reg,\ logic_imm,logics_imm,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\ adr,bfm,rev,alu_dsp_reg,\
shift_imm,shift_reg") shift_imm,shift_reg")
(not (eq_attr "conds" "set"))) (not (eq_attr "conds" "set")))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_conds" 4 (define_insn_reservation "pj4_alu_conds" 4
(and (eq_attr "tune" "marvell_pj4") (and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "alu_imm,alus_imm,alu_reg,alus_reg,\ (eq_attr "type" "alu_imm,alus_imm,alu_sreg,alus_sreg,\
logic_imm,logics_imm,logic_reg,logics_reg,\ logic_imm,logics_imm,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\ adr,bfm,rev,alu_dsp_reg,\
shift_imm,shift_reg") shift_imm,shift_reg")
(eq_attr "conds" "set")) (eq_attr "conds" "set"))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
......
gcc/config/arm/thumb1.md
...@@ -81,8 +81,8 @@ ...@@ -81,8 +81,8 @@
operands[2] = GEN_INT (INTVAL (operands[2]) - offset); operands[2] = GEN_INT (INTVAL (operands[2]) - offset);
} }
[(set_attr "length" "2,2,2,2,2,2,2,4,4,4") [(set_attr "length" "2,2,2,2,2,2,2,4,4,4")
(set_attr "type" "alus_imm,alus_imm,alus_reg,alus_reg,alus_reg, (set_attr "type" "alus_imm,alus_imm,alus_sreg,alus_sreg,alus_sreg,
alus_reg,alus_reg,multiple,multiple,multiple")] alus_sreg,alus_sreg,multiple,multiple,multiple")]
) )
;; Reloading and elimination of the frame pointer can ;; Reloading and elimination of the frame pointer can
...@@ -118,7 +118,7 @@ ...@@ -118,7 +118,7 @@
"sub\\t%0, %1, %2" "sub\\t%0, %1, %2"
[(set_attr "length" "2") [(set_attr "length" "2")
(set_attr "conds" "set") (set_attr "conds" "set")
(set_attr "type" "alus_reg")] (set_attr "type" "alus_sreg")]
) )
; Unfortunately with the Thumb the '&'/'0' trick can fails when operands ; Unfortunately with the Thumb the '&'/'0' trick can fails when operands
......
gcc/config/arm/thumb2.md
...@@ -1117,7 +1117,7 @@ ...@@ -1117,7 +1117,7 @@
"%I3%!\\t%0, %1, %2" "%I3%!\\t%0, %1, %2"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "length" "2") (set_attr "length" "2")
(set_attr "type" "alu_reg")] (set_attr "type" "alu_sreg")]
) )
(define_insn "*thumb2_shiftsi3_short" (define_insn "*thumb2_shiftsi3_short"
...@@ -1171,7 +1171,7 @@ ...@@ -1171,7 +1171,7 @@
" "
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "length" "2") (set_attr "length" "2")
(set_attr "type" "alu_reg")] (set_attr "type" "alu_sreg")]
) )
(define_insn "*thumb2_subsi_short" (define_insn "*thumb2_subsi_short"
...@@ -1183,7 +1183,7 @@ ...@@ -1183,7 +1183,7 @@
"sub%!\\t%0, %1, %2" "sub%!\\t%0, %1, %2"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "length" "2") (set_attr "length" "2")
(set_attr "type" "alu_reg")] (set_attr "type" "alu_sreg")]
) )
(define_peephole2 (define_peephole2
...@@ -1236,7 +1236,7 @@ ...@@ -1236,7 +1236,7 @@
" "
[(set_attr "conds" "set") [(set_attr "conds" "set")
(set_attr "length" "2,2,4") (set_attr "length" "2,2,4")
(set_attr "type" "alu_reg")] (set_attr "type" "alu_sreg")]
) )
(define_insn "*thumb2_addsi3_compare0_scratch" (define_insn "*thumb2_addsi3_compare0_scratch"
...@@ -1261,7 +1261,7 @@ ...@@ -1261,7 +1261,7 @@
" "
[(set_attr "conds" "set") [(set_attr "conds" "set")
(set_attr "length" "2,2,4,4") (set_attr "length" "2,2,4,4")
(set_attr "type" "alus_imm,alus_reg,alus_imm,alus_reg")] (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_sreg")]
) )
(define_insn "*thumb2_mulsi_short" (define_insn "*thumb2_mulsi_short"
...@@ -1367,7 +1367,7 @@ ...@@ -1367,7 +1367,7 @@
"neg%!\t%0, %1" "neg%!\t%0, %1"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "length" "2") (set_attr "length" "2")
(set_attr "type" "alu_reg")] (set_attr "type" "alu_sreg")]
) )
; Constants for op 2 will never be given to these patterns. ; Constants for op 2 will never be given to these patterns.
......
gcc/config/arm/types.md
...@@ -35,17 +35,19 @@ ...@@ -35,17 +35,19 @@
; alu_imm any arithmetic instruction that doesn't have a shifted ; alu_imm any arithmetic instruction that doesn't have a shifted
; operand and has an immediate operand. This ; operand and has an immediate operand. This
; excludes MOV, MVN and RSB(S) immediate. ; excludes MOV, MVN and RSB(S) immediate.
; alu_reg any arithmetic instruction that doesn't have a shifted ; alu_sreg any arithmetic instruction that doesn't have a shifted
; or an immediate operand. This excludes ; or an immediate operand. This excludes
; MOV and MVN but includes MOVT. This is also the default. ; MOV and MVN but includes MOVT. This also excludes
; DSP-kind instructions. This is also the default.
; alu_shift_imm any arithmetic instruction that has a source operand ; alu_shift_imm any arithmetic instruction that has a source operand
; shifted by a constant. This excludes simple shifts. ; shifted by a constant. This excludes simple shifts.
; alu_shift_reg as alu_shift_imm, with the shift amount specified in a ; alu_shift_reg as alu_shift_imm, with the shift amount specified in a
; register. ; register.
; alu_dsp_reg any DSP-kind instruction like QSUB8.
; alus_ext From ARMv8-A: as alu_ext, setting condition flags. ; alus_ext From ARMv8-A: as alu_ext, setting condition flags.
; AArch64 Only. ; AArch64 Only.
; alus_imm as alu_imm, setting condition flags. ; alus_imm as alu_imm, setting condition flags.
; alus_reg as alu_reg, setting condition flags. ; alus_sreg as alu_sreg, setting condition flags.
; alus_shift_imm as alu_shift_imm, setting condition flags. ; alus_shift_imm as alu_shift_imm, setting condition flags.
; alus_shift_reg as alu_shift_reg, setting condition flags. ; alus_shift_reg as alu_shift_reg, setting condition flags.
; bfm bitfield move operation. ; bfm bitfield move operation.
...@@ -540,12 +542,13 @@ ...@@ -540,12 +542,13 @@
adr,\ adr,\
alu_ext,\ alu_ext,\
alu_imm,\ alu_imm,\
alu_reg,\ alu_sreg,\
alu_shift_imm,\ alu_shift_imm,\
alu_shift_reg,\ alu_shift_reg,\
alu_dsp_reg,\
alus_ext,\ alus_ext,\
alus_imm,\ alus_imm,\
alus_reg,\ alus_sreg,\
alus_shift_imm,\ alus_shift_imm,\
alus_shift_reg,\ alus_shift_reg,\
bfm,\ bfm,\
......
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