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riscv-gcc-1
Commit 1d29a58d by Bob Wilson Committed by Bob Wilson
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* config/xtensa/xtensa.md (<u>mulsidi3): Use a temporary register. 

From-SVN: r139750
parent d2155632
Showing with 7 additions and 2 deletions
gcc/ChangeLog
2008-08-28 Bob Wilson <bob.wilson@acm.org>
* config/xtensa/xtensa.md (<u>mulsidi3): Use a temporary register.
2008-08-28 Adam Nemet <anemet@caviumnetworks.com> 2008-08-28 Adam Nemet <anemet@caviumnetworks.com>
* config/mips/mips.h (ISA_HAS_BBIT): New macro. * config/mips/mips.h (ISA_HAS_BBIT): New macro.
......
gcc/config/xtensa/xtensa.md
...@@ -222,10 +222,11 @@ ...@@ -222,10 +222,11 @@
(any_extend:DI (match_operand:SI 2 "register_operand"))))] (any_extend:DI (match_operand:SI 2 "register_operand"))))]
"TARGET_MUL32_HIGH" "TARGET_MUL32_HIGH"
{ {
emit_insn (gen_mulsi3 (gen_lowpart (SImode, operands[0]), rtx temp = gen_reg_rtx (SImode);
operands[1], operands[2])); emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
emit_insn (gen_<u>mulsi3_highpart (gen_highpart (SImode, operands[0]), emit_insn (gen_<u>mulsi3_highpart (gen_highpart (SImode, operands[0]),
operands[1], operands[2])); operands[1], operands[2]));
emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), temp));
DONE; DONE;
}) })
......
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