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Commit 1ce485ec by Jan Hubicka Committed by Jan Hubicka
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i386.md (negs?2): Rewrite to expanders... 

	* i386.md (negs?2): Rewrite to expanders, new patterns and splitters
	to support integer registers and memory.
	(abss?2_integer): Likewise.

From-SVN: r30596
parent 65c93378
Showing with 211 additions and 10 deletions
gcc/ChangeLog
Fri Nov 19 06:32:19 CET 1999 Jan Hubicka <hubicka@freesoft.cz> Fri Nov 19 06:32:19 CET 1999 Jan Hubicka <hubicka@freesoft.cz>
* i386.md (negs?2): Rewrite to expanders, new patterns and splitters
to support integer registers and memory.
(abss?2_integer): Likewise.
* i386.h (enum reg_class): Add FLOAT_INT_REGS. * i386.h (enum reg_class): Add FLOAT_INT_REGS.
(REG_CLASS_NAMES): Likewise. (REG_CLASS_NAMES): Likewise.
......
gcc/config/i386/i386.md
...@@ -4931,18 +4931,120 @@ ...@@ -4931,18 +4931,120 @@
"neg{b}\\t%0" "neg{b}\\t%0"
[(set_attr "type" "negnot")]) [(set_attr "type" "negnot")])
;; Changing of sign for FP values is duable using integer unit too.
(define_insn "negsf2" (define_insn "negsf2"
[(set (match_operand:SF 0 "nonimmediate_operand" "=frm")
(neg:SF (match_operand:SF 1 "nonimmediate_operand" "0")))
(clobber (reg:CC 17))]
"TARGET_80387"
"#")
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(neg:SF (match_operand:SF 1 "register_operand" "")))
(clobber (reg:CC 17))]
"TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
[(set (match_dup 0)
(neg:SF (match_dup 1)))]
"")
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(neg:SF (match_operand:SF 1 "register_operand" "")))
(clobber (reg:CC 17))]
"TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
[(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
(clobber (reg:CC 17))])]
"operands[1] = GEN_INT (0x80000000);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
(define_split
[(set (match_operand 0 "memory_operand" "")
(neg (match_operand 1 "memory_operand" "")))
(clobber (reg:CC 17))]
"TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
[(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
(clobber (reg:CC 17))])]
"
{
int size = GET_MODE_SIZE (GET_MODE (operands[1]));
/* XFmode's size is 12, but only 10 bytes are used. */
if (size == 12)
size = 10;
operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
operands[0] = adj_offsettable_operand (operands[0], size - 1);
operands[1] = GEN_INT (0x80);
}")
(define_insn "negdf2"
[(set (match_operand:DF 0 "nonimmediate_operand" "=frm")
(neg:DF (match_operand:DF 1 "nonimmediate_operand" "0")))
(clobber (reg:CC 17))]
"TARGET_80387"
"#")
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(neg:DF (match_operand:DF 1 "register_operand" "")))
(clobber (reg:CC 17))]
"TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
[(set (match_dup 0)
(neg:DF (match_dup 1)))]
"")
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(neg:DF (match_operand:DF 1 "register_operand" "")))
(clobber (reg:CC 17))]
"TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
[(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
(clobber (reg:CC 17))])]
"operands[4] = GEN_INT (0x80000000);
split_di (operands+0, 1, operands+2, operands+3);")
(define_insn "negxf2"
[(set (match_operand:XF 0 "nonimmediate_operand" "=frm")
(neg:XF (match_operand:XF 1 "nonimmediate_operand" "0")))
(clobber (reg:CC 17))]
"TARGET_80387"
"#")
(define_split
[(set (match_operand:XF 0 "register_operand" "")
(neg:XF (match_operand:XF 1 "register_operand" "")))
(clobber (reg:CC 17))]
"TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
[(set (match_dup 0)
(neg:XF (match_dup 1)))]
"")
(define_split
[(set (match_operand:XF 0 "register_operand" "")
(neg:XF (match_operand:XF 1 "register_operand" "")))
(clobber (reg:CC 17))]
"TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
[(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
(clobber (reg:CC 17))])]
"operands[1] = GEN_INT (0x8000);
operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]) + 2);")
;; Conditionize these after reload. If they matches before reload, we
;; lose the clobber and ability to use integer instructions.
(define_insn "*negsf2_1"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(neg:SF (match_operand:SF 1 "register_operand" "0")))] (neg:SF (match_operand:SF 1 "register_operand" "0")))]
"TARGET_80387" "TARGET_80387 && reload_completed"
"fchs" "fchs"
[(set_attr "type" "fsgn") [(set_attr "type" "fsgn")
(set_attr "ppro_uops" "few")]) (set_attr "ppro_uops" "few")])
(define_insn "negdf2" (define_insn "*negdf2_1"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(neg:DF (match_operand:DF 1 "register_operand" "0")))] (neg:DF (match_operand:DF 1 "register_operand" "0")))]
"TARGET_80387" "TARGET_80387 && reload_completed"
"fchs" "fchs"
[(set_attr "type" "fsgn") [(set_attr "type" "fsgn")
(set_attr "ppro_uops" "few")]) (set_attr "ppro_uops" "few")])
...@@ -4956,10 +5058,10 @@ ...@@ -4956,10 +5058,10 @@
[(set_attr "type" "fsgn") [(set_attr "type" "fsgn")
(set_attr "ppro_uops" "few")]) (set_attr "ppro_uops" "few")])
(define_insn "negxf2" (define_insn "*negxf2_1"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(neg:XF (match_operand:XF 1 "register_operand" "0")))] (neg:XF (match_operand:XF 1 "register_operand" "0")))]
"TARGET_80387" "TARGET_80387 && reload_completed"
"fchs" "fchs"
[(set_attr "type" "fsgn") [(set_attr "type" "fsgn")
(set_attr "ppro_uops" "few")]) (set_attr "ppro_uops" "few")])
...@@ -4985,16 +5087,112 @@ ...@@ -4985,16 +5087,112 @@
;; Absolute value instructions ;; Absolute value instructions
(define_insn "abssf2" (define_insn "abssf2"
[(set (match_operand:SF 0 "nonimmediate_operand" "=frm")
(abs:SF (match_operand:SF 1 "nonimmediate_operand" "0")))
(clobber (reg:CC 17))]
"TARGET_80387"
"#")
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(abs:SF (match_operand:SF 1 "register_operand" "")))
(clobber (reg:CC 17))]
"TARGET_80387 && FP_REGNO_P (REGNO (operands[0]))"
[(set (match_dup 0)
(abs:SF (match_dup 1)))]
"")
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(abs:SF (match_operand:SF 1 "register_operand" "")))
(clobber (reg:CC 17))]
"TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
(clobber (reg:CC 17))])]
"operands[1] = GEN_INT (~0x80000000);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
(define_split
[(set (match_operand 0 "memory_operand" "")
(abs (match_operand 1 "memory_operand" "")))
(clobber (reg:CC 17))]
"TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
[(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
(clobber (reg:CC 17))])]
"
{
int size = GET_MODE_SIZE (GET_MODE (operands[1]));
/* XFmode's size is 12, but only 10 bytes are used. */
if (size == 12)
size = 10;
operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
operands[0] = adj_offsettable_operand (operands[0], size - 1);
operands[1] = GEN_INT (~0x80);
}")
(define_insn "absdf2"
[(set (match_operand:DF 0 "nonimmediate_operand" "=frm")
(abs:DF (match_operand:DF 1 "nonimmediate_operand" "0")))]
"TARGET_80387"
"#")
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(abs:DF (match_operand:DF 1 "register_operand" "")))
(clobber (reg:CC 17))]
"TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
[(set (match_dup 0)
(abs:DF (match_dup 1)))]
"")
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(abs:DF (match_operand:DF 1 "register_operand" "")))
(clobber (reg:CC 17))]
"TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
[(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
(clobber (reg:CC 17))])]
"operands[4] = GEN_INT (~0x80000000);
split_di (operands+0, 1, operands+2, operands+3);")
(define_insn "absxf2"
[(set (match_operand:XF 0 "nonimmediate_operand" "=frm")
(abs:XF (match_operand:XF 1 "nonimmediate_operand" "0")))
(clobber (reg:CC 17))]
"TARGET_80387"
"#")
(define_split
[(set (match_operand:XF 0 "register_operand" "")
(abs:XF (match_operand:XF 1 "register_operand" "")))
(clobber (reg:CC 17))]
"TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
[(set (match_dup 0)
(abs:XF (match_dup 1)))]
"")
(define_split
[(set (match_operand:XF 0 "register_operand" "")
(abs:XF (match_operand:XF 1 "register_operand" "")))
(clobber (reg:CC 17))]
"TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
(clobber (reg:CC 17))])]
"operands[1] = GEN_INT (~0x8000);
operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]) + 2);")
(define_insn "*abssf2_1"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(abs:SF (match_operand:SF 1 "register_operand" "0")))] (abs:SF (match_operand:SF 1 "register_operand" "0")))]
"TARGET_80387" "TARGET_80387 && reload_completed"
"fabs" "fabs"
[(set_attr "type" "fsgn")]) [(set_attr "type" "fsgn")])
(define_insn "absdf2" (define_insn "*absdf2_1"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(abs:DF (match_operand:DF 1 "register_operand" "0")))] (abs:DF (match_operand:DF 1 "register_operand" "0")))]
"TARGET_80387" "TARGET_80387 && reload_completed"
"fabs" "fabs"
[(set_attr "type" "fsgn")]) [(set_attr "type" "fsgn")])
...@@ -5006,10 +5204,10 @@ ...@@ -5006,10 +5204,10 @@
"fabs" "fabs"
[(set_attr "type" "fsgn")]) [(set_attr "type" "fsgn")])
(define_insn "absxf2" (define_insn "*absxf2_1"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(abs:XF (match_operand:XF 1 "register_operand" "0")))] (abs:XF (match_operand:XF 1 "register_operand" "0")))]
"TARGET_80387" "TARGET_80387 && reload_completed"
"fabs" "fabs"
[(set_attr "type" "fsgn")]) [(set_attr "type" "fsgn")])
......
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