Skip to content

R
riscv-gcc-1
Commit 1cc82d13 by Richard Earnshaw Committed by Richard Earnshaw
Options

* arm.md (addsi3_carryin_shift): Add missing register constraints. 

From-SVN: r74694
parent 649a1a47
Showing with 8 additions and 4 deletions
gcc/ChangeLog
2003-12-16 Richard Earnshaw <rearnsha@arm.com>
* arm.md (addsi3_carryin_shift): Add missing register constraints.
2003-12-16 Loren James Rittle <ljrittle@acm.org>
* testsuite/g++.old-deja/g++.eh/badalloc1.C: Tweak to
......
gcc/config/arm/arm.md
......@@ -792,13 +792,13 @@
)
(define_insn "*addsi3_carryin_shift"
[(set (match_operand:SI 0 "s_register_operand" "")
[(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
(plus:SI
(match_operator:SI 2 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "")
(match_operand:SI 4 "reg_or_int_operand" "")])
(match_operand:SI 1 "s_register_operand" ""))))]
[(match_operand:SI 3 "s_register_operand" "r")
(match_operand:SI 4 "reg_or_int_operand" "rM")])
(match_operand:SI 1 "s_register_operand" "r"))))]
"TARGET_ARM"
"adc%?\\t%0, %1, %3%S2"
[(set_attr "conds" "use")]
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment