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Commit 1ca2e73f by Richard Henderson Committed by Richard Henderson
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alpha.md (fix_truncdfsi2, [...]): Remove the define_expands, but keep the insns and splits. 

        * alpha.md (fix_truncdfsi2, fix_truncsfsi2): Remove the define_expands,
        but keep the insns and splits.  Adjust so when the ultimate destination
        is memory, use cvtql.

From-SVN: r21322
parent bd80fbde
Showing with 64 additions and 59 deletions
gcc/ChangeLog
Tue Jul 21 08:56:42 1998 Richard Henderson <rth@cygnus.com>
* alpha.md (fix_truncdfsi2, fix_truncsfsi2): Remove the define_expands,
but keep the insns and splits. Adjust so when the ultimate destination
is memory, use cvtql.
Tue Jul 21 08:55:09 1998 Richard Henderson <rth@cygnus.com> Tue Jul 21 08:55:09 1998 Richard Henderson <rth@cygnus.com>
* flow.c (regno_uninitialized): Fixed regs are never uninitialized. * flow.c (regno_uninitialized): Fixed regs are never uninitialized.
......
gcc/config/alpha/alpha.md
...@@ -1794,58 +1794,60 @@ ...@@ -1794,58 +1794,60 @@
;; instruction. To allow combine et al to do useful things, we keep the ;; instruction. To allow combine et al to do useful things, we keep the
;; operation as a unit until after reload, at which point we split the ;; operation as a unit until after reload, at which point we split the
;; instructions. ;; instructions.
;;
;; Note that we (attempt to) only consider this optimization when the
;; ultimate destination is memory. If we will be doing further integer
;; processing, it is cheaper to do the truncation in the int regs.
(define_insn "*cvtql"
[(set (match_operand:SI 0 "register_operand" "=f")
(unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")] 5))]
"TARGET_FP"
"cvtql%` %R1,%0"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
(define_split (define_split
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "memory_operand" "")
(fix:SI (match_operand:DF 1 "reg_or_fp0_operand" ""))) (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
(clobber (match_scratch:DI 2 ""))] (clobber (match_scratch:DI 2 ""))
(clobber (match_scratch:SI 3 ""))]
"TARGET_FP && reload_completed" "TARGET_FP && reload_completed"
[(set (match_dup 2) (fix:DI (match_dup 1))) [(set (match_dup 2) (fix:DI (match_dup 1)))
(set (match_dup 0) (unspec:SI [(match_dup 2)] 5))] (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
(set (match_dup 0) (match_dup 3))]
"") "")
;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
(define_split (define_split
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "memory_operand" "")
(fix:SI (match_operand:DF 1 "reg_or_fp0_operand" "")))] (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
(clobber (match_scratch:DI 2 ""))]
"TARGET_FP && reload_completed" "TARGET_FP && reload_completed"
[(set (match_dup 2) (fix:DI (match_dup 1))) [(set (match_dup 2) (fix:DI (match_dup 1)))
(set (match_dup 0) (unspec:SI [(match_dup 2)] 5))] (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
"operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));") (set (match_dup 0) (match_dup 3))]
;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
"operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=f") [(set (match_operand:SI 0 "memory_operand" "=m")
(unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")] 5))] (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
"TARGET_FP" (clobber (match_scratch:DI 2 "=&f"))
"cvtql%` %R1,%0" (clobber (match_scratch:SI 3 "=&f"))]
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
(define_insn "fix_truncdfsi2_tp"
[(set (match_operand:SI 0 "register_operand" "=&f")
(fix:SI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))
(clobber (match_scratch:DI 2 "=&f"))]
"TARGET_FP && alpha_tp == ALPHA_TP_INSN" "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
"#" "#"
[(set_attr "type" "fadd") [(set_attr "type" "fadd")
(set_attr "trap" "yes")]) (set_attr "trap" "yes")])
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=f") [(set (match_operand:SI 0 "memory_operand" "=m")
(fix:SI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
(clobber (match_scratch:DI 2 "=f"))]
"TARGET_FP && alpha_tp != ALPHA_TP_INSN" "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
"#" "#"
[(set_attr "type" "fadd") [(set_attr "type" "fadd")
(set_attr "trap" "yes")]) (set_attr "trap" "yes")])
(define_expand "fix_truncdfsi2"
[(set (match_operand:SI 0 "register_operand" "=f")
(fix:SI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
"TARGET_FP"
"{ if (alpha_tp == ALPHA_TP_INSN)
{ emit_insn(gen_fix_truncdfsi2_tp(operands[0], operands[1])); DONE; }
}")
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "register_operand" "=&f") [(set (match_operand:DI 0 "register_operand" "=&f")
(fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
...@@ -1865,53 +1867,50 @@ ...@@ -1865,53 +1867,50 @@
;; Likewise between SFmode and SImode. ;; Likewise between SFmode and SImode.
(define_split (define_split
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "memory_operand" "")
(fix:SI (float_extend:DF (subreg:SI (fix:DI (float_extend:DF
(match_operand:SF 1 "reg_or_fp0_operand" "")))) (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
(clobber (match_scratch:DI 2 ""))] (clobber (match_scratch:DI 2 ""))
(clobber (match_scratch:SI 3 ""))]
"TARGET_FP && reload_completed" "TARGET_FP && reload_completed"
[(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1)))) [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
(set (match_dup 0) (unspec:SI [(match_dup 2)] 5))] (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
(set (match_dup 0) (match_dup 3))]
"") "")
;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
(define_split (define_split
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "memory_operand" "")
(fix:SI (float_extend:DF (subreg:SI (fix:DI (float_extend:DF
(match_operand:SF 1 "reg_or_fp0_operand" ""))))] (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
(clobber (match_scratch:DI 2 ""))]
"TARGET_FP && reload_completed" "TARGET_FP && reload_completed"
[(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1)))) [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
(set (match_dup 0) (unspec:SI [(match_dup 2)] 5))] (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
"operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));") (set (match_dup 0) (match_dup 3))]
;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
(define_insn "fix_truncsfsi2_tp" "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
[(set (match_operand:SI 0 "register_operand" "=&f")
(fix:SI (float_extend:DF (define_insn ""
(match_operand:SF 1 "reg_or_fp0_operand" "fG")))) [(set (match_operand:SI 0 "memory_operand" "=m")
(clobber (match_scratch:DI 2 "=&f"))] (subreg:SI (fix:DI (float_extend:DF
(match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
(clobber (match_scratch:DI 2 "=&f"))
(clobber (match_scratch:SI 3 "=&f"))]
"TARGET_FP && alpha_tp == ALPHA_TP_INSN" "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
"#" "#"
[(set_attr "type" "fadd") [(set_attr "type" "fadd")
(set_attr "trap" "yes")]) (set_attr "trap" "yes")])
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=f") [(set (match_operand:SI 0 "memory_operand" "=m")
(fix:SI (float_extend:DF (subreg:SI (fix:DI (float_extend:DF
(match_operand:SF 1 "reg_or_fp0_operand" "fG"))))] (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
(clobber (match_scratch:DI 2 "=f"))]
"TARGET_FP && alpha_tp != ALPHA_TP_INSN" "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
"#" "#"
[(set_attr "type" "fadd") [(set_attr "type" "fadd")
(set_attr "trap" "yes")]) (set_attr "trap" "yes")])
(define_expand "fix_truncsfsi2"
[(set (match_operand:SI 0 "register_operand" "=f")
(fix:SI (float_extend:DF
(match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
"TARGET_FP"
"{ if (alpha_tp == ALPHA_TP_INSN)
{ emit_insn(gen_fix_truncsfsi2_tp(operands[0], operands[1])); DONE; }
}")
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "register_operand" "=&f") [(set (match_operand:DI 0 "register_operand" "=&f")
(fix:DI (float_extend:DF (fix:DI (float_extend:DF
......
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