[Patch AArch64] Fix register constraints for lane intrinsics.

gcc/
	* config/aarch64/aarch64-simd.md
	(aarch64_sqdml<SBINQOPS:as>l_n<mode>_internal): Use
	<vwx> iterator to ensure correct register choice.
	(aarch64_sqdml<SBINQOPS:as>l2_n<mode>_internal): Likewise.
	(aarch64_sqdmull_n<mode>): Likewise.
	(aarch64_sqdmull2_n<mode>_internal): Likewise.
	* config/aarch64/arm_neon.h
	(vml<as><q>_lane<q>_<su>16): Use 'x' constraint for element vector.
	(vml<as><q>_n_<su>16): Likewise.
	(vml<as>l_high_lane<q>_<su>16): Likewise.
	(vml<as>l_high_n_<su>16): Likewise.
	(vml<as>l_lane<q>_<su>16): Likewise.
	(vml<as>l_n_<su>16): Likewise.
	(vmul<q>_lane<q>_<su>16): Likewise.
	(vmul<q>_n_<su>16): Likewise.
	(vmull_lane<q>_<su>16): Likewise.
	(vmull_n_<su>16): Likewise.
	(vmull_high_lane<q>_<su>16): Likewise.
	(vmull_high_n_<su>16): Likewise.
	(vqrdmulh<q>_n_s16): Likewise.

From-SVN: r202322

gcc/ChangeLog

+2013-09-06  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* config/aarch64/aarch64-simd.md
+	(aarch64_sqdml<SBINQOPS:as>l_n<mode>_internal): Use
+	<vwx> iterator to ensure correct register choice.
+	(aarch64_sqdml<SBINQOPS:as>l2_n<mode>_internal): Likewise.
+	(aarch64_sqdmull_n<mode>): Likewise.
+	(aarch64_sqdmull2_n<mode>_internal): Likewise.
+	* config/aarch64/arm_neon.h
+	(vml<as><q>_lane<q>_<su>16): Use 'x' constraint for element vector.
+	(vml<as><q>_n_<su>16): Likewise.
+	(vml<as>l_high_lane<q>_<su>16): Likewise.
+	(vml<as>l_high_n_<su>16): Likewise.
+	(vml<as>l_lane<q>_<su>16): Likewise.
+	(vml<as>l_n_<su>16): Likewise.
+	(vmul<q>_lane<q>_<su>16): Likewise.
+	(vmul<q>_n_<su>16): Likewise.
+	(vmull_lane<q>_<su>16): Likewise.
+	(vmull_n_<su>16): Likewise.
+	(vmull_high_lane<q>_<su>16): Likewise.
+	(vmull_high_n_<su>16): Likewise.
+	(vqrdmulh<q>_n_s16): Likewise.
+
 2013-09-06  Tejas Belagod  <tejas.belagod@arm.com>
 
 	* config/aarch64/arm_neon.h: Fix all vdup<bhsd_lane<q> intrinsics to

gcc/config/aarch64/aarch64-simd.md

@@ -2797,7 +2797,7 @@
 		      (match_operand:VD_HSI 2 "register_operand" "w"))
 		(sign_extend:<VWIDE>
 		  (vec_duplicate:VD_HSI
-		    (match_operand:<VEL> 3 "register_operand" "w"))))
+		    (match_operand:<VEL> 3 "register_operand" "<vwx>"))))
 	      (const_int 1))))]
   "TARGET_SIMD"
   "sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[0]"
@@ -2955,7 +2955,7 @@
                   (match_operand:VQ_HSI 4 "vect_par_cnst_hi_half" "")))
 	      (sign_extend:<VWIDE>
                 (vec_duplicate:<VHALF>
-		  (match_operand:<VEL> 3 "register_operand" "w"))))
+		  (match_operand:<VEL> 3 "register_operand" "<vwx>"))))
 	    (const_int 1))))]
   "TARGET_SIMD"
   "sqdml<SBINQOPS:as>l2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[0]"
@@ -3083,7 +3083,7 @@
 		 (match_operand:VD_HSI 1 "register_operand" "w"))
 	       (sign_extend:<VWIDE>
                  (vec_duplicate:VD_HSI
-                   (match_operand:<VEL> 2 "register_operand" "w")))
+                   (match_operand:<VEL> 2 "register_operand" "<vwx>")))
 	       )
 	     (const_int 1)))]
   "TARGET_SIMD"
@@ -3193,7 +3193,7 @@
                    (match_operand:VQ_HSI 3 "vect_par_cnst_hi_half" "")))
 	       (sign_extend:<VWIDE>
                  (vec_duplicate:<VHALF>
-                   (match_operand:<VEL> 2 "register_operand" "w")))
+                   (match_operand:<VEL> 2 "register_operand" "<vwx>")))
 	       )
 	     (const_int 1)))]
   "TARGET_SIMD"