re PR target/14552 (compiled trivial vector intrinsic code is inefficient)
PR target/14552 * config/i386/mmx.md (*mov<mode>_internal_rex64"): Adjust register allocator preferences for "y" and "r" class registers. ("*mov<mode>_internal"): Ditto. ("*movv2sf_internal_rex64"): Ditto. ("*movv2sf_internal"): Ditto. testsuite/ChangeLog: PR target/14552 * gcc.target/i386/pr14552.c: New test. From-SVN: r133354
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gcc/testsuite/gcc.target/i386/pr14552.c
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