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Commit 1b187f36 by Richard Sandiford Committed by Richard Sandiford
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[AArch64] Use SVE BIC for conditional arithmetic 

This patch uses BIC to pattern-match conditional AND with an inverted
third input.  It also adds extra tests for AND, ORR and EOR.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>
	    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
	* config/aarch64/aarch64-sve.md (*cond_bic<mode>_2)
	(*cond_bic<mode>_any): New patterns.

gcc/testsuite/
	* gcc.target/aarch64/sve/cond_logical_1.c: New test.
	* gcc.target/aarch64/sve/cond_logical_1_run.c: Likewise.
	* gcc.target/aarch64/sve/cond_logical_2.c: Likewise.
	* gcc.target/aarch64/sve/cond_logical_2_run.c: Likewise.
	* gcc.target/aarch64/sve/cond_logical_3.c: Likewise.
	* gcc.target/aarch64/sve/cond_logical_3_run.c: Likewise.
	* gcc.target/aarch64/sve/cond_logical_4.c: Likewise.
	* gcc.target/aarch64/sve/cond_logical_4_run.c: Likewise.
	* gcc.target/aarch64/sve/cond_logical_5.c: Likewise.
	* gcc.target/aarch64/sve/cond_logical_5_run.c: Likewise.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>

From-SVN: r274480
parent d113ece6
Showing with 548 additions and 0 deletions
gcc/ChangeLog
2019-08-14 Richard Sandiford <richard.sandiford@arm.com> 2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
* config/aarch64/aarch64-sve.md (*cond_bic<mode>_2)
(*cond_bic<mode>_any): New patterns.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.c (aarch64_print_operand): Allow %e to * config/aarch64/aarch64.c (aarch64_print_operand): Allow %e to
take the equivalent mask, as well as a bit count. take the equivalent mask, as well as a bit count.
......
gcc/config/aarch64/aarch64-sve.md
...@@ -2274,6 +2274,50 @@ ...@@ -2274,6 +2274,50 @@
} }
) )
;; Predicated integer BIC, merging with the first input.
(define_insn "*cond_bic<mode>_2"
[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
(unspec:SVE_I
[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
(and:SVE_I
(not:SVE_I (match_operand:SVE_I 3 "register_operand" "w, w"))
(match_operand:SVE_I 2 "register_operand" "0, w"))
(match_dup 2)]
UNSPEC_SEL))]
"TARGET_SVE"
"@
bic\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
movprfx\t%0, %2\;bic\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
[(set_attr "movprfx" "*,yes")]
)
;; Predicated integer BIC, merging with an independent value.
(define_insn_and_rewrite "*cond_bic<mode>_any"
[(set (match_operand:SVE_I 0 "register_operand" "=&w, &w, &w, ?&w")
(unspec:SVE_I
[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl")
(and:SVE_I
(not:SVE_I (match_operand:SVE_I 3 "register_operand" "w, w, w, w"))
(match_operand:SVE_I 2 "register_operand" "0, w, w, w"))
(match_operand:SVE_I 4 "aarch64_simd_reg_or_zero" "Dz, Dz, 0, w")]
UNSPEC_SEL))]
"TARGET_SVE && !rtx_equal_p (operands[2], operands[4])"
"@
movprfx\t%0.<Vetype>, %1/z, %0.<Vetype>\;bic\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;bic\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
movprfx\t%0.<Vetype>, %1/m, %2.<Vetype>\;bic\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
#"
"&& reload_completed
&& register_operand (operands[4], <MODE>mode)
&& !rtx_equal_p (operands[0], operands[4])"
{
emit_insn (gen_vcond_mask_<mode><vpred> (operands[0], operands[2],
operands[4], operands[1]));
operands[4] = operands[2] = operands[0];
}
[(set_attr "movprfx" "yes")]
)
;; ------------------------------------------------------------------------- ;; -------------------------------------------------------------------------
;; ---- [INT] Shifts ;; ---- [INT] Shifts
;; ------------------------------------------------------------------------- ;; -------------------------------------------------------------------------
......
gcc/testsuite/ChangeLog
2019-08-14 Richard Sandiford <richard.sandiford@arm.com> 2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
* gcc.target/aarch64/sve/cond_logical_1.c: New test.
* gcc.target/aarch64/sve/cond_logical_1_run.c: Likewise.
* gcc.target/aarch64/sve/cond_logical_2.c: Likewise.
* gcc.target/aarch64/sve/cond_logical_2_run.c: Likewise.
* gcc.target/aarch64/sve/cond_logical_3.c: Likewise.
* gcc.target/aarch64/sve/cond_logical_3_run.c: Likewise.
* gcc.target/aarch64/sve/cond_logical_4.c: Likewise.
* gcc.target/aarch64/sve/cond_logical_4_run.c: Likewise.
* gcc.target/aarch64/sve/cond_logical_5.c: Likewise.
* gcc.target/aarch64/sve/cond_logical_5_run.c: Likewise.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
* gcc.target/aarch64/sve/cond_uxt_1.c: New test. * gcc.target/aarch64/sve/cond_uxt_1.c: New test.
* gcc.target/aarch64/sve/cond_uxt_1_run.c: Likewise. * gcc.target/aarch64/sve/cond_uxt_1_run.c: Likewise.
......
gcc/testsuite/gcc.target/aarch64/sve/cond_logical_1.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize" } */
#include <stdint.h>
#define bit_and(A, B) ((A) & (B))
#define bit_or(A, B) ((A) | (B))
#define bit_xor(A, B) ((A) ^ (B))
#define bit_bic(A, B) ((A) & ~(B))
#define DEF_LOOP(TYPE, OP) \
void __attribute__ ((noinline, noclone)) \
test_##TYPE##_##OP (TYPE *__restrict r, \
TYPE *__restrict a, \
TYPE *__restrict b, \
TYPE *__restrict c, int n) \
{ \
for (int i = 0; i < n; ++i) \
r[i] = a[i] < 20 ? OP (b[i], c[i]) : b[i]; \
}
#define TEST_TYPE(T, TYPE) \
T (TYPE, bit_and) \
T (TYPE, bit_or) \
T (TYPE, bit_xor) \
T (TYPE, bit_bic)
#define TEST_ALL(T) \
TEST_TYPE (T, int8_t) \
TEST_TYPE (T, uint8_t) \
TEST_TYPE (T, int16_t) \
TEST_TYPE (T, uint16_t) \
TEST_TYPE (T, int32_t) \
TEST_TYPE (T, uint32_t) \
TEST_TYPE (T, int64_t) \
TEST_TYPE (T, uint64_t)
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-not {\tmov\tz[^,]*z} } } */
/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
/* { dg-final { scan-assembler-not {\tsel\t} } } */
gcc/testsuite/gcc.target/aarch64/sve/cond_logical_1_run.c 0 → 100644
/* { dg-do run { target aarch64_sve_hw } } */
/* { dg-options "-O2 -ftree-vectorize" } */
#include "cond_logical_1.c"
#define N 99
#define TEST_LOOP(TYPE, OP) \
{ \
TYPE r[N], a[N], b[N], c[N]; \
for (int i = 0; i < N; ++i) \
{ \
a[i] = (i & 1 ? i : 3 * i); \
b[i] = (i >> 4) << (i & 15); \
c[i] = ((i + 2) % 3) * (i + 1); \
asm volatile ("" ::: "memory"); \
} \
test_##TYPE##_##OP (r, a, b, c, N); \
for (int i = 0; i < N; ++i) \
{ \
TYPE expected = a[i] < 20 ? OP (b[i], c[i]) : b[i]; \
if (r[i] != expected) \
__builtin_abort (); \
asm volatile ("" ::: "memory"); \
} \
}
int
main (void)
{
TEST_ALL (TEST_LOOP)
return 0;
}
gcc/testsuite/gcc.target/aarch64/sve/cond_logical_2.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize" } */
#include <stdint.h>
#define bit_and(A, B) ((A) & (B))
#define bit_or(A, B) ((A) | (B))
#define bit_xor(A, B) ((A) ^ (B))
#define bit_bic(A, B) ((A) & ~(B))
#define DEF_LOOP(TYPE, OP) \
void __attribute__ ((noinline, noclone)) \
test_##TYPE##_##OP (TYPE *__restrict r, \
TYPE *__restrict a, \
TYPE *__restrict b, \
TYPE *__restrict c, int n) \
{ \
for (int i = 0; i < n; ++i) \
r[i] = a[i] < 20 ? OP (b[i], c[i]) : c[i]; \
}
#define TEST_TYPE(T, TYPE) \
T (TYPE, bit_and) \
T (TYPE, bit_or) \
T (TYPE, bit_xor) \
T (TYPE, bit_bic)
#define TEST_ALL(T) \
TEST_TYPE (T, int8_t) \
TEST_TYPE (T, uint8_t) \
TEST_TYPE (T, int16_t) \
TEST_TYPE (T, uint16_t) \
TEST_TYPE (T, int32_t) \
TEST_TYPE (T, uint32_t) \
TEST_TYPE (T, int64_t) \
TEST_TYPE (T, uint64_t)
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-not {\tmov\tz[^,]*z} } } */
/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
/* There's no BICR or equivalent, so the BIC functions need a select. */
/* { dg-final { scan-assembler-times {\tsel\t} 8 } } */
gcc/testsuite/gcc.target/aarch64/sve/cond_logical_2_run.c 0 → 100644
/* { dg-do run { target aarch64_sve_hw } } */
/* { dg-options "-O2 -ftree-vectorize" } */
#include "cond_logical_2.c"
#define N 99
#define TEST_LOOP(TYPE, OP) \
{ \
TYPE r[N], a[N], b[N], c[N]; \
for (int i = 0; i < N; ++i) \
{ \
a[i] = (i & 1 ? i : 3 * i); \
b[i] = (i >> 4) << (i & 15); \
c[i] = ((i + 2) % 3) * (i + 1); \
asm volatile ("" ::: "memory"); \
} \
test_##TYPE##_##OP (r, a, b, c, N); \
for (int i = 0; i < N; ++i) \
{ \
TYPE expected = a[i] < 20 ? OP (b[i], c[i]) : c[i]; \
if (r[i] != expected) \
__builtin_abort (); \
asm volatile ("" ::: "memory"); \
} \
}
int
main (void)
{
TEST_ALL (TEST_LOOP)
return 0;
}
gcc/testsuite/gcc.target/aarch64/sve/cond_logical_3.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize" } */
#include <stdint.h>
#define bit_and(A, B) ((A) & (B))
#define bit_or(A, B) ((A) | (B))
#define bit_xor(A, B) ((A) ^ (B))
#define bit_bic(A, B) ((A) & ~(B))
#define DEF_LOOP(TYPE, OP) \
void __attribute__ ((noinline, noclone)) \
test_##TYPE##_##OP (TYPE *__restrict r, \
TYPE *__restrict a, \
TYPE *__restrict b, \
TYPE *__restrict c, int n) \
{ \
for (int i = 0; i < n; ++i) \
r[i] = a[i] < 20 ? OP (b[i], c[i]) : a[i]; \
}
#define TEST_TYPE(T, TYPE) \
T (TYPE, bit_and) \
T (TYPE, bit_or) \
T (TYPE, bit_xor) \
T (TYPE, bit_bic)
#define TEST_ALL(T) \
TEST_TYPE (T, int8_t) \
TEST_TYPE (T, uint8_t) \
TEST_TYPE (T, int16_t) \
TEST_TYPE (T, uint16_t) \
TEST_TYPE (T, int32_t) \
TEST_TYPE (T, uint32_t) \
TEST_TYPE (T, int64_t) \
TEST_TYPE (T, uint64_t)
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b\n} 8 } } */
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 8 } } */
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 8 } } */
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d\n} 8 } } */
/* { dg-final { scan-assembler-not {\tmov\tz[^,]*z} } } */
/* { dg-final { scan-assembler-not {\tsel\t} } } */
gcc/testsuite/gcc.target/aarch64/sve/cond_logical_3_run.c 0 → 100644
/* { dg-do run { target aarch64_sve_hw } } */
/* { dg-options "-O2 -ftree-vectorize" } */
#include "cond_logical_3.c"
#define N 99
#define TEST_LOOP(TYPE, OP) \
{ \
TYPE r[N], a[N], b[N], c[N]; \
for (int i = 0; i < N; ++i) \
{ \
a[i] = (i & 1 ? i : 3 * i); \
b[i] = (i >> 4) << (i & 15); \
c[i] = ((i + 2) % 3) * (i + 1); \
asm volatile ("" ::: "memory"); \
} \
test_##TYPE##_##OP (r, a, b, c, N); \
for (int i = 0; i < N; ++i) \
{ \
TYPE expected = a[i] < 20 ? OP (b[i], c[i]) : a[i]; \
if (r[i] != expected) \
__builtin_abort (); \
asm volatile ("" ::: "memory"); \
} \
}
int
main (void)
{
TEST_ALL (TEST_LOOP)
return 0;
}
gcc/testsuite/gcc.target/aarch64/sve/cond_logical_4.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize" } */
#include <stdint.h>
#define bit_and(A, B) ((A) & (B))
#define bit_or(A, B) ((A) | (B))
#define bit_xor(A, B) ((A) ^ (B))
#define bit_bic(A, B) ((A) & ~(B))
#define DEF_LOOP(TYPE, OP) \
void __attribute__ ((noinline, noclone)) \
test_##TYPE##_##OP (TYPE *__restrict r, \
TYPE *__restrict a, \
TYPE *__restrict b, \
TYPE *__restrict c, int n) \
{ \
for (int i = 0; i < n; ++i) \
r[i] = a[i] < 20 ? OP (b[i], c[i]) : 42; \
}
#define TEST_TYPE(T, TYPE) \
T (TYPE, bit_and) \
T (TYPE, bit_or) \
T (TYPE, bit_xor) \
T (TYPE, bit_bic)
#define TEST_ALL(T) \
TEST_TYPE (T, int8_t) \
TEST_TYPE (T, uint8_t) \
TEST_TYPE (T, int16_t) \
TEST_TYPE (T, uint16_t) \
TEST_TYPE (T, int32_t) \
TEST_TYPE (T, uint32_t) \
TEST_TYPE (T, int64_t) \
TEST_TYPE (T, uint64_t)
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-not {\tmov\tz[^,]*z} } } */
/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
/* { dg-final { scan-assembler-times {\tsel\t} 32 } } */
gcc/testsuite/gcc.target/aarch64/sve/cond_logical_4_run.c 0 → 100644
/* { dg-do run { target aarch64_sve_hw } } */
/* { dg-options "-O2 -ftree-vectorize" } */
#include "cond_logical_4.c"
#define N 99
#define TEST_LOOP(TYPE, OP) \
{ \
TYPE r[N], a[N], b[N], c[N]; \
for (int i = 0; i < N; ++i) \
{ \
a[i] = (i & 1 ? i : 3 * i); \
b[i] = (i >> 4) << (i & 15); \
c[i] = ((i + 2) % 3) * (i + 1); \
asm volatile ("" ::: "memory"); \
} \
test_##TYPE##_##OP (r, a, b, c, N); \
for (int i = 0; i < N; ++i) \
{ \
TYPE expected = a[i] < 20 ? OP (b[i], c[i]) : 42; \
if (r[i] != expected) \
__builtin_abort (); \
asm volatile ("" ::: "memory"); \
} \
}
int
main (void)
{
TEST_ALL (TEST_LOOP)
return 0;
}
gcc/testsuite/gcc.target/aarch64/sve/cond_logical_5.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize" } */
#include <stdint.h>
#define bit_and(A, B) ((A) & (B))
#define bit_or(A, B) ((A) | (B))
#define bit_xor(A, B) ((A) ^ (B))
#define bit_bic(A, B) ((A) & ~(B))
#define DEF_LOOP(TYPE, OP) \
void __attribute__ ((noinline, noclone)) \
test_##TYPE##_##OP (TYPE *__restrict r, \
TYPE *__restrict a, \
TYPE *__restrict b, \
TYPE *__restrict c, int n) \
{ \
for (int i = 0; i < n; ++i) \
r[i] = a[i] < 20 ? OP (b[i], c[i]) : 0; \
}
#define TEST_TYPE(T, TYPE) \
T (TYPE, bit_and) \
T (TYPE, bit_or) \
T (TYPE, bit_xor) \
T (TYPE, bit_bic)
#define TEST_ALL(T) \
TEST_TYPE (T, int8_t) \
TEST_TYPE (T, uint8_t) \
TEST_TYPE (T, int16_t) \
TEST_TYPE (T, uint16_t) \
TEST_TYPE (T, int32_t) \
TEST_TYPE (T, uint32_t) \
TEST_TYPE (T, int64_t) \
TEST_TYPE (T, uint64_t)
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tbic\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.b, p[0-7]/z, z[0-9]+\.b\n} 8 } } */
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 8 } } */
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 8 } } */
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.d, p[0-7]/z, z[0-9]+\.d\n} 8 } } */
/* { dg-final { scan-assembler-not {\tmov\tz[^,]*z} } } */
/* { dg-final { scan-assembler-not {\tsel\t} } } */
gcc/testsuite/gcc.target/aarch64/sve/cond_logical_5_run.c 0 → 100644
/* { dg-do run { target aarch64_sve_hw } } */
/* { dg-options "-O2 -ftree-vectorize" } */
#include "cond_logical_5.c"
#define N 99
#define TEST_LOOP(TYPE, OP) \
{ \
TYPE r[N], a[N], b[N], c[N]; \
for (int i = 0; i < N; ++i) \
{ \
a[i] = (i & 1 ? i : 3 * i); \
b[i] = (i >> 4) << (i & 15); \
c[i] = ((i + 2) % 3) * (i + 1); \
asm volatile ("" ::: "memory"); \
} \
test_##TYPE##_##OP (r, a, b, c, N); \
for (int i = 0; i < N; ++i) \
{ \
TYPE expected = a[i] < 20 ? OP (b[i], c[i]) : 0; \
if (r[i] != expected) \
__builtin_abort (); \
asm volatile ("" ::: "memory"); \
} \
}
int
main (void)
{
TEST_ALL (TEST_LOOP)
return 0;
}
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