Commit 19e43cbc by Michael Meissner

Add some gcc_asserts for vector extract processing.

2020-02-03  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some
	gcc_asserts.
parent d60c25fa
2020-02-03 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some
gcc_asserts.
2020-02-03 Segher Boessenkool <segher@kernel.crashing.org> 2020-02-03 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/constraints.md: Improve documentation. * config/rs6000/constraints.md: Improve documentation.
......
...@@ -6768,6 +6768,9 @@ rs6000_adjust_vec_address (rtx scalar_reg, ...@@ -6768,6 +6768,9 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx new_addr; rtx new_addr;
bool valid_addr_p; bool valid_addr_p;
gcc_assert (!reg_mentioned_p (base_tmp, addr));
gcc_assert (!reg_mentioned_p (base_tmp, element));
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */ /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC); gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
...@@ -6777,6 +6780,10 @@ rs6000_adjust_vec_address (rtx scalar_reg, ...@@ -6777,6 +6780,10 @@ rs6000_adjust_vec_address (rtx scalar_reg,
element_offset = GEN_INT (INTVAL (element) * scalar_size); element_offset = GEN_INT (INTVAL (element) * scalar_size);
else else
{ {
/* All insns should use the 'Q' constraint (address is a single register)
if the element number is not a constant. */
gcc_assert (REG_P (addr) || SUBREG_P (addr));
int byte_shift = exact_log2 (scalar_size); int byte_shift = exact_log2 (scalar_size);
gcc_assert (byte_shift >= 0); gcc_assert (byte_shift >= 0);
......
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