re PR target/82580 (Optimize comparisons for __int128 on x86-64)

	PR target/82580
	* config/i386/i386.md (setcc + movzbl to xor + setcc): New peephole2.
	(setcc + and to xor + setcc): New peephole2.

	* gcc.target/i386/pr82580.c: Use {\msbb} instead of "sbb" in
	scan-assembler-times.  Check that there are no movzb* instructions
	if lp64.

From-SVN: r253884

gcc/ChangeLog

+2017-10-19  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/82580
+	* config/i386/i386.md (setcc + movzbl to xor + setcc): New peephole2.
+	(setcc + and to xor + setcc): New peephole2.
+
 2017-10-19  Tom de Vries  <tom@codesourcery.com>
 
 	* doc/sourcebuild.texi (Test Directives, Variants of

gcc/config/i386/i386.md

@@ -12300,6 +12300,34 @@
   ix86_expand_clear (operands[3]);
 })
 
+(define_peephole2
+  [(set (reg FLAGS_REG) (match_operand 0))
+   (parallel [(set (reg FLAGS_REG) (match_operand 1))
+	      (match_operand 5)])
+   (set (match_operand:QI 2 "register_operand")
+	(match_operator:QI 3 "ix86_comparison_operator"
+	  [(reg FLAGS_REG) (const_int 0)]))
+   (set (match_operand 4 "any_QIreg_operand")
+	(zero_extend (match_dup 2)))]
+  "(peep2_reg_dead_p (4, operands[2])
+    || operands_match_p (operands[2], operands[4]))
+   && ! reg_overlap_mentioned_p (operands[4], operands[0])
+   && ! reg_overlap_mentioned_p (operands[4], operands[1])
+   && ! reg_set_p (operands[4], operands[5])
+   && refers_to_regno_p (FLAGS_REG, operands[1], (rtx *)NULL)
+   && peep2_regno_dead_p (0, FLAGS_REG)"
+  [(set (match_dup 6) (match_dup 0))
+   (parallel [(set (match_dup 7) (match_dup 1))
+	      (match_dup 5)])
+   (set (strict_low_part (match_dup 8))
+	(match_dup 3))]
+{
+  operands[6] = gen_rtx_REG (GET_MODE (operands[0]), FLAGS_REG);
+  operands[7] = gen_rtx_REG (GET_MODE (operands[1]), FLAGS_REG);
+  operands[8] = gen_lowpart (QImode, operands[4]);
+  ix86_expand_clear (operands[4]);
+})
+
 ;; Similar, but match zero extend with andsi3.
 
 (define_peephole2
@@ -12345,6 +12373,35 @@
   operands[6] = gen_lowpart (QImode, operands[3]);
   ix86_expand_clear (operands[3]);
 })
+
+(define_peephole2
+  [(set (reg FLAGS_REG) (match_operand 0))
+   (parallel [(set (reg FLAGS_REG) (match_operand 1))
+	      (match_operand 5)])
+   (set (match_operand:QI 2 "register_operand")
+	(match_operator:QI 3 "ix86_comparison_operator"
+	  [(reg FLAGS_REG) (const_int 0)]))
+   (parallel [(set (match_operand 4 "any_QIreg_operand")
+		   (zero_extend (match_dup 2)))
+	      (clobber (reg:CC FLAGS_REG))])]
+  "(peep2_reg_dead_p (4, operands[2])
+    || operands_match_p (operands[2], operands[4]))
+   && ! reg_overlap_mentioned_p (operands[4], operands[0])
+   && ! reg_overlap_mentioned_p (operands[4], operands[1])
+   && ! reg_set_p (operands[4], operands[5])
+   && refers_to_regno_p (FLAGS_REG, operands[1], (rtx *)NULL)
+   && peep2_regno_dead_p (0, FLAGS_REG)"
+  [(set (match_dup 6) (match_dup 0))
+   (parallel [(set (match_dup 7) (match_dup 1))
+	      (match_dup 5)])
+   (set (strict_low_part (match_dup 8))
+	(match_dup 3))]
+{
+  operands[6] = gen_rtx_REG (GET_MODE (operands[0]), FLAGS_REG);
+  operands[7] = gen_rtx_REG (GET_MODE (operands[1]), FLAGS_REG);
+  operands[8] = gen_lowpart (QImode, operands[4]);
+  ix86_expand_clear (operands[4]);
+})
 
 ;; Call instructions.
 

gcc/testsuite/ChangeLog

+2017-10-19  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/82580
+	* gcc.target/i386/pr82580.c: Use {\msbb} instead of "sbb" in
+	scan-assembler-times.  Check that there are no movzb* instructions
+	if lp64.
+
 2017-10-19  Tom de Vries  <tom@codesourcery.com>
 
 	* gcc.dg/tree-ssa/ldist-27.c: Use dg-require-stack-size.

gcc/testsuite/gcc.target/i386/pr82580.c

@@ -35,4 +35,5 @@ void f21 (S x, S y) { if (x >= y) bar (); }
 void f22 (S x, S y) { if (x < y) bar (); }
 void f23 (S x, S y) { if (x <= y) bar (); }
 
-/* { dg-final { scan-assembler-times "sbb" 16 } } */
+/* { dg-final { scan-assembler-times {\msbb} 16 } } */
+/* { dg-final { scan-assembler-not {\mmovzb} { target lp64 } } } */