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riscv-gcc-1
Commit 17ea6633 by Michael Meissner
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Do not allow DFs to use 2 register addressing if -msoft-float 

From-SVN: r9441
parent 2ac53349
Showing with 1 additions and 0 deletions
gcc/config/rs6000/rs6000.h
...@@ -1438,6 +1438,7 @@ struct rs6000_args {int words, fregno, nargs_prototype; }; ...@@ -1438,6 +1438,7 @@ struct rs6000_args {int words, fregno, nargs_prototype; };
} \ } \
else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
&& GET_CODE (XEXP (X, 1)) != CONST_INT \ && GET_CODE (XEXP (X, 1)) != CONST_INT \
&& (TARGET_HARD_FLOAT || (MODE) != DFmode) \
&& (MODE) != DImode && (MODE) != TImode) \ && (MODE) != DImode && (MODE) != TImode) \
{ \ { \
(X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \ (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \
......
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