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riscv-gcc-1
Commit 17b706a6 by Jeff Law
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h8300.c (adds_subs_operand): Fix thinko in last change. 

        * h8300/h8300.c (adds_subs_operand): Fix thinko in last change.

        * h8300/h8300.md (subhi3): Turn into a define_expand.
        (subhi3 using adds_subs): New pattern.
        (H8300 subhi): Derived from old subhi pattern.  Simplified.
        (H8300H subhi): Likewise.
        (subsi using adds_subs): New pattern.  Only used on H8300H.
        (subsi_h8300): Allow "a" registers as destination.
        (subsi_h8300h): Allow "a" registers as destination.  Simplify.

        * h8300/h8300.md (bcs_qiqi, bcs_hihi, bs_hiqi): Fix thinkos
        in last change.

From-SVN: r11754
parent a3ec0d4b
Showing with 85 additions and 32 deletions
gcc/config/h8300/h8300.c
......@@ -444,11 +444,11 @@ adds_subs_operand (op, mode)
return 1;
if (TARGET_H8300H
&& INTVAL (op) != 7
&& (INTVAL (op) <= 8 || INTVAL (op) >= 0))
&& (INTVAL (op) <= 8 && INTVAL (op) >= 0))
return 1;
if (TARGET_H8300H
&& INTVAL (op) != -7
&& (INTVAL (op) >= -8 || INTVAL (op) <= 0))
&& (INTVAL (op) >= -8 && INTVAL (op) <= 0))
return 1;
}
return 0;
......
gcc/config/h8300/h8300.md
......@@ -39,6 +39,9 @@
;; Some move patterns have conditions which check that one operand
;; is a register. Shouldn't all of them have such a condition?
;; Consistently use "a" constraint. Probably makes little difference
;; in the generated code, but it's easy to do.
;; Loading some 32bit integer constants could be done more
;; efficiently. For example loading the value 4 as a 32bit
;; is normally done via mov.l #4,erX. sub.l erX,erX, inc.l #4,erX
......@@ -682,23 +685,54 @@
;; h8300h: subs operates on the 32bit register. We can use it because we don't
;; use the e0-7 registers.
;; ??? 4 can be handled in one insn on the 300h.
;; ??? The fourth alternative can use sub.w on the 300h.
;; ??? Should the 'n' constraint be an 'i' here?
(define_insn "subhi3"
[(set (match_operand:HI 0 "register_operand" "=ra,ra,ra,r")
(minus:HI (match_operand:HI 1 "general_operand" "0,0,0,0")
(match_operand:HI 2 "nonmemory_operand" "K,M,ra,n")))]
(define_expand "subhi3"
[(set (match_operand:HI 0 "register_operand" "")
(minus:HI (match_operand:HI 1 "general_operand" "")
(match_operand:HI 2 "nonmemory_operand" "")))]
""
"")
;; Specialized version using adds/subs. This must come before
;; the more general patterns below. This may not be needed
;; due to instruction canonicalization.
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=ra")
(minus:HI (match_operand:HI 1 "register_operand" "r")
(match_operand:HI 2 "adds_subs_operand" "i")))]
""
"*
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
return output_adds_subs (operands);
}"
[(set_attr "type" "arith")
(set_attr "length" "4")
(set_attr "cc" "none_0hit")])
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=ra,&ra")
(minus:HI (match_operand:HI 1 "general_operand" "0,0")
(match_operand:HI 2 "nonmemory_operand" "ra,n")))]
"TARGET_H8300"
"@
subs %T2,%T0
subs #2,%T0\;subs %M2,%T0
sub.w %T2,%T0
add.b %E2,%s0\;addx %F2,%t0 ; -%0"
[(set_attr "type" "multi")
(set_attr "length" "2,4,2,4")
(set_attr "cc" "none_0hit,none_0hit,set_zn_c0,clobber")])
[(set_attr "type" "arith,multi")
(set_attr "length" "2,4")
(set_attr "cc" "set_zn_c0,clobber")])
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=ra,&ra")
(minus:HI (match_operand:HI 1 "general_operand" "0,0")
(match_operand:HI 2 "nonmemory_operand" "ra,i")))]
"TARGET_H8300H"
"@
sub.w %T2,%T0
sub.w %T2,%T0"
[(set_attr "type" "arith")
(set_attr "length" "2,4")
(set_attr "cc" "set_zn_c0,set_zn_c0")])
(define_expand "subsi3"
[(set (match_operand:SI 0 "register_operand" "")
......@@ -717,21 +751,34 @@
(set_attr "length" "6")
(set_attr "cc" "clobber")])
;; ??? 4 can be handled in one insn on the 300h.
;; Specialized version using adds/subs. This must come before
;; the more general patterns below. This may not be needed
;; due to instruction canonicalization.
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=ra")
(minus:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "adds_subs_operand" "i")))]
"TARGET_H8300H"
"*
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
return output_adds_subs (operands);
}"
[(set_attr "type" "arith")
(set_attr "length" "4")
(set_attr "cc" "none_0hit")])
(define_insn "subsi3_h8300h"
[(set (match_operand:SI 0 "register_operand" "=ra,ra,ra,r")
(minus:SI (match_operand:SI 1 "general_operand" "0,0,0,0")
(match_operand:SI 2 "nonmemory_operand" "K,M,ra,n")))]
[(set (match_operand:SI 0 "register_operand" "=ra,ra")
(minus:SI (match_operand:SI 1 "general_operand" "0,0")
(match_operand:SI 2 "nonmemory_operand" "ra,i")))]
"TARGET_H8300H"
"@
subs %T2,%T0
subs #2,%T0\;subs %E2,%T0
sub.l %S2,%S0
sub.l %S2,%S0"
[(set_attr "type" "multi")
(set_attr "length" "2,4,2,6")
(set_attr "cc" "none_0hit,none_0hit,set_zn_c0,set_zn_c0")])
[(set_attr "type" "arith")
(set_attr "length" "2,6")
(set_attr "cc" "set_zn_c0,set_zn_c0")])
;; ----------------------------------------------------------------------
;; MULTIPLY INSTRUCTIONS
......@@ -1774,15 +1821,17 @@
int branch_length = get_attr_length (insn);
if (! register_operand (operands[2], QImode))
branch_length -= 4;
else
branch_length -= 2;
output_asm_insn(\"bld %Z3,%Y2\", operands);
if (branch_length == 2)
return \"b%d1 %l0\";
return \"%d1 %l0\";
else if (branch_length == 4)
return \"b%d1 %l0:16\";
return \"%d1 %l0:16\";
else
return \"b%g1 %L0\;jmp @%l0\;%L0:\";
return \"%g1 %L0\;jmp @%l0\;%L0:\";
}"
[(set_attr "type" "bcs")
(set_attr "cc" "clobber")])
......@@ -1806,15 +1855,17 @@
int branch_length = get_attr_length (insn);
if (! register_operand (operands[2], QImode))
branch_length -= 4;
else
branch_length -= 2;
output_asm_insn(\"bld %Z3,%Y2\", operands);
if (branch_length == 2)
return \"b%d1 %l0\";
return \"%d1 %l0\";
else if (branch_length == 4)
return \"b%d1 %l0:16\";
return \"%d1 %l0:16\";
else
return \"b%g1 %L0\;jmp @%l0\;%L0:\";
return \"%g1 %L0\;jmp @%l0\;%L0:\";
}"
[(set_attr "type" "bcs")
(set_attr "cc" "clobber")])
......@@ -1838,15 +1889,17 @@
int branch_length = get_attr_length (insn);
if (! register_operand (operands[2], QImode))
branch_length -= 4;
else
branch_length -= 2;
output_asm_insn(\"bld %Z3,%Y2\", operands);
if (branch_length == 2)
return \"b%d1 %l0\";
return \"%d1 %l0\";
else if (branch_length == 4)
return \"b%d1 %l0:16\";
return \"%d1 %l0:16\";
else
return \"b%g1 %L0\;jmp @%l0\;%L0:\";
return \"%g1 %L0\;jmp @%l0\;%L0:\";
}"
[(set_attr "type" "bcs")
(set_attr "cc" "clobber")])
......
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