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Commit 16cf8119 by David S. Miller Committed by David S. Miller
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sparc.md (define_insn addx_extend): Rename to addx_extend_sp64, only allow when TARGET_ARCH64. 

	* config/sparc/sparc.md (define_insn addx_extend): Rename to
	addx_extend_sp64, only allow when TARGET_ARCH64.
	(define_insn addx_extend_sp32 and split): Version that works when
	not TARGET_ARCH64.
	(define_insn subx_extend): Likewise.
	(define_split adddi3 and subdi3 with zero extension): Fixup and
	correct bugs when not TARGET_ARCH64.

From-SVN: r21677
parent abf82aab
Showing with 78 additions and 18 deletions
gcc/ChangeLog
Tue Aug 11 22:42:01 1998 David S. Miller <davem@pierdol.cobaltmicro.com>
* config/sparc/sparc.md (define_insn addx_extend): Rename to
addx_extend_sp64, only allow when TARGET_ARCH64.
(define_insn addx_extend_sp32 and split): Version that works when
not TARGET_ARCH64.
(define_insn subx_extend): Likewise.
(define_split adddi3 and subdi3 with zero extension): Fixup and
correct bugs when not TARGET_ARCH64.
Tue Aug 11 16:04:34 1998 John Carr <jfc@mit.edu> Tue Aug 11 16:04:34 1998 John Carr <jfc@mit.edu>
* except.c (set_exception_lang_code, set_exception_version_code): * except.c (set_exception_lang_code, set_exception_version_code):
......
gcc/config/sparc/sparc.md
...@@ -4444,12 +4444,34 @@ movtf_is_ok: ...@@ -4444,12 +4444,34 @@ movtf_is_ok:
[(set_attr "type" "unary") [(set_attr "type" "unary")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "*addx_extend" (define_insn "*addx_extend_sp32"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
(match_operand:SI 2 "arith_operand" "rI")) (match_operand:SI 2 "arith_operand" "rI"))
(ltu:SI (reg:CC_NOOV 100) (const_int 0))))] (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
"" "! TARGET_ARCH64"
"#"
[(set_attr "type" "unary")
(set_attr "length" "2")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
(match_operand:SI 2 "arith_operand" ""))
(ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
"! TARGET_ARCH64 && reload_completed"
[(set (match_dup 3) (plus:SI (plus:SI (match_dup 1) (match_dup 2))
(ltu:SI (reg:CC_NOOV 100) (const_int 0))))
(set (match_dup 4) (const_int 0))]
"operands[3] = gen_lowpart (SImode, operands[0]);
operands[4] = gen_highpart (SImode, operands[1]);")
(define_insn "*addx_extend_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
(plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
(match_operand:SI 2 "arith_operand" "rI"))
(ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
"TARGET_ARCH64"
"addx\\t%r1, %2, %0" "addx\\t%r1, %2, %0"
[(set_attr "type" "unary") [(set_attr "type" "unary")
(set_attr "length" "1")]) (set_attr "length" "1")])
...@@ -4464,16 +4486,38 @@ movtf_is_ok: ...@@ -4464,16 +4486,38 @@ movtf_is_ok:
[(set_attr "type" "unary") [(set_attr "type" "unary")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "*subx_extend" (define_insn "*subx_extend_sp64"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
(match_operand:SI 2 "arith_operand" "rI")) (match_operand:SI 2 "arith_operand" "rI"))
(ltu:SI (reg:CC_NOOV 100) (const_int 0))))] (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
"" "TARGET_ARCH64"
"subx\\t%r1, %2, %0" "subx\\t%r1, %2, %0"
[(set_attr "type" "unary") [(set_attr "type" "unary")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "*subx_extend"
[(set (match_operand:DI 0 "register_operand" "=r")
(minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
(match_operand:SI 2 "arith_operand" "rI"))
(ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
"! TARGET_ARCH64"
"#"
[(set_attr "type" "unary")
(set_attr "length" "2")])
(define_split
[(set (match_operand:DI 0 "register_operand" "=r")
(minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
(match_operand:SI 2 "arith_operand" "rI"))
(ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
"! TARGET_ARCH64 && reload_completed"
[(set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 2))
(ltu:SI (reg:CC_NOOV 100) (const_int 0))))
(set (match_dup 4) (const_int 0))]
"operands[3] = gen_lowpart (SImode, operands[0]);
operands[4] = gen_highpart (SImode, operands[0]);")
;; This is only for splits at the moment. ;; This is only for splits at the moment.
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -4487,8 +4531,8 @@ movtf_is_ok: ...@@ -4487,8 +4531,8 @@ movtf_is_ok:
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
(match_operand:DI 2 "register_operand" "r"))) (match_operand:DI 2 "register_operand" "r")))
(clobber (reg:CC 100))] (clobber (reg:CC 100))]
"! TARGET_ARCH64" "! TARGET_ARCH64"
"#" "#"
...@@ -4501,14 +4545,17 @@ movtf_is_ok: ...@@ -4501,14 +4545,17 @@ movtf_is_ok:
(match_operand:DI 2 "register_operand" ""))) (match_operand:DI 2 "register_operand" "")))
(clobber (reg:CC 100))] (clobber (reg:CC 100))]
"! TARGET_ARCH64" "! TARGET_ARCH64"
[(set (reg:CC_NOOV 100) [(parallel [(set (reg:CC_NOOV 100)
(compare:CC_NOOV (plus:SI (match_dup 3) (match_dup 1)) (compare:CC_NOOV (plus:SI (match_dup 3) (match_dup 1))
(const_int 0))) (const_int 0)))
(set (match_dup 0) (set (match_dup 5) (plus:SI (match_dup 3) (match_dup 1)))])
(set (match_dup 6)
(plus:SI (plus:SI (match_dup 4) (const_int 0)) (plus:SI (plus:SI (match_dup 4) (const_int 0))
(ltu:SI (reg:CC_NOOV 100) (const_int 0))))] (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
"operands[3] = gen_lowpart (SImode, operands[2]); "operands[3] = gen_lowpart (SImode, operands[2]);
operands[4] = gen_highpart (SImode, operands[2]);") operands[4] = gen_highpart (SImode, operands[2]);
operands[5] = gen_lowpart (SImode, operands[0]);
operands[6] = gen_highpart (SImode, operands[0]);")
(define_insn "*adddi3_sp64" (define_insn "*adddi3_sp64"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -4672,14 +4719,17 @@ movtf_is_ok: ...@@ -4672,14 +4719,17 @@ movtf_is_ok:
(zero_extend:DI (match_operand:SI 2 "register_operand" "")))) (zero_extend:DI (match_operand:SI 2 "register_operand" ""))))
(clobber (reg:CC 100))] (clobber (reg:CC 100))]
"! TARGET_ARCH64" "! TARGET_ARCH64"
[(set (reg:CC_NOOV 100) [(parallel [(set (reg:CC_NOOV 100)
(compare:CC_NOOV (minus:SI (match_dup 3) (match_dup 2)) (compare:CC_NOOV (minus:SI (match_dup 3) (match_dup 2))
(const_int 0))) (const_int 0)))
(set (match_dup 0) (set (match_dup 5) (minus:SI (match_dup 3) (match_dup 2)))])
(plus:SI (plus:SI (match_dup 4) (const_int 0)) (set (match_dup 6)
(ltu:SI (reg:CC_NOOV 100) (const_int 0))))] (minus:SI (minus:SI (match_dup 4) (const_int 0))
(ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
"operands[3] = gen_lowpart (SImode, operands[1]); "operands[3] = gen_lowpart (SImode, operands[1]);
operands[4] = gen_highpart (SImode, operands[1]);") operands[4] = gen_highpart (SImode, operands[1]);
operands[5] = gen_lowpart (SImode, operands[0]);
operands[6] = gen_highpart (SImode, operands[0]);")
(define_insn "*subdi3_sp64" (define_insn "*subdi3_sp64"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
......
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