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riscv-gcc-1
Commit 1598bfb0 by Segher Boessenkool Committed by Segher Boessenkool
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rs6000: Delete Fv2 

<Fv2> always is "wa".


	* config/rs6000/rs6000.md (define_mode_attr Fv2): Delete.
	(rest of file): Adjust.

From-SVN: r271918
parent 11d7bd36
Showing with 41 additions and 41 deletions
gcc/ChangeLog
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org> 2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.md (define_mode_attr Fv2): Delete.
(rest of file): Adjust.
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/vsx.md (define_mode_attr VS_64reg): Delete. * config/rs6000/vsx.md (define_mode_attr VS_64reg): Delete.
(*vsx_extract_<P:mode>_<VSX_D:mode>_load): Adjust. (*vsx_extract_<P:mode>_<VSX_D:mode>_load): Adjust.
(vsx_splat_<mode>_reg): Adjust. (vsx_splat_<mode>_reg): Adjust.
......
gcc/config/rs6000/rs6000.md
...@@ -528,11 +528,6 @@ ...@@ -528,11 +528,6 @@
; format. ; format.
(define_mode_attr Fv [(SF "ww") (DF "wa") (DI "wa")]) (define_mode_attr Fv [(SF "ww") (DF "wa") (DI "wa")])
; SF/DF constraint for arithmetic on VSX registers. This is intended to be
; used for DFmode instructions added in ISA 2.06 (power7) and SFmode
; instructions added in ISA 2.07 (power8)
(define_mode_attr Fv2 [(SF "wa") (DF "wa") (DI "wa")])
; Which isa is needed for those float instructions? ; Which isa is needed for those float instructions?
(define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")]) (define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")])
...@@ -4638,9 +4633,9 @@ ...@@ -4638,9 +4633,9 @@
"") "")
(define_insn "*add<mode>3_fpr" (define_insn "*add<mode>3_fpr"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>") [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
(plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>") (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,wa")
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))] (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"@ "@
fadd<Ftrad> %0,%1,%2 fadd<Ftrad> %0,%1,%2
...@@ -4656,9 +4651,9 @@ ...@@ -4656,9 +4651,9 @@
"") "")
(define_insn "*sub<mode>3_fpr" (define_insn "*sub<mode>3_fpr"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>") [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
(minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>") (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))] (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"@ "@
fsub<Ftrad> %0,%1,%2 fsub<Ftrad> %0,%1,%2
...@@ -4674,9 +4669,9 @@ ...@@ -4674,9 +4669,9 @@
"") "")
(define_insn "*mul<mode>3_fpr" (define_insn "*mul<mode>3_fpr"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>") [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
(mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>") (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,wa")
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))] (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"@ "@
fmul<Ftrad> %0,%1,%2 fmul<Ftrad> %0,%1,%2
...@@ -4700,9 +4695,9 @@ ...@@ -4700,9 +4695,9 @@
}) })
(define_insn "*div<mode>3_fpr" (define_insn "*div<mode>3_fpr"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>") [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
(div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>") (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))] (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"@ "@
fdiv<Ftrad> %0,%1,%2 fdiv<Ftrad> %0,%1,%2
...@@ -4711,8 +4706,8 @@ ...@@ -4711,8 +4706,8 @@
(set_attr "isa" "*,<Fisa>")]) (set_attr "isa" "*,<Fisa>")])
(define_insn "*sqrt<mode>2_internal" (define_insn "*sqrt<mode>2_internal"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>") [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
(sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")))] (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT && TARGET_PPC_GPOPT" "TARGET_HARD_FLOAT && TARGET_PPC_GPOPT"
"@ "@
fsqrt<Ftrad> %0,%1 fsqrt<Ftrad> %0,%1
...@@ -4739,8 +4734,8 @@ ...@@ -4739,8 +4734,8 @@
;; Floating point reciprocal approximation ;; Floating point reciprocal approximation
(define_insn "fre<Fs>" (define_insn "fre<Fs>"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>") [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")] (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")]
UNSPEC_FRES))] UNSPEC_FRES))]
"TARGET_<FFRE>" "TARGET_<FFRE>"
"@ "@
...@@ -4750,8 +4745,8 @@ ...@@ -4750,8 +4745,8 @@
(set_attr "isa" "*,<Fisa>")]) (set_attr "isa" "*,<Fisa>")])
(define_insn "*rsqrt<mode>2" (define_insn "*rsqrt<mode>2"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>") [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")] (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")]
UNSPEC_RSQRT))] UNSPEC_RSQRT))]
"RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)" "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
"@ "@
...@@ -4763,8 +4758,8 @@ ...@@ -4763,8 +4758,8 @@
;; Floating point comparisons ;; Floating point comparisons
(define_insn "*cmp<mode>_fpr" (define_insn "*cmp<mode>_fpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y") [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
(compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>") (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))] (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"@ "@
fcmpu %0,%1,%2 fcmpu %0,%1,%2
...@@ -13374,11 +13369,11 @@ ...@@ -13374,11 +13369,11 @@
"") "")
(define_insn "*fma<mode>4_fpr" (define_insn "*fma<mode>4_fpr"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>") [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa")
(fma:SFDF (fma:SFDF
(match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>,<Fv2>") (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,wa,wa")
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0") (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0")
(match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>")))] (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa")))]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"@ "@
fmadd<Ftrad> %0,%1,%2,%3 fmadd<Ftrad> %0,%1,%2,%3
...@@ -13398,11 +13393,11 @@ ...@@ -13398,11 +13393,11 @@
"") "")
(define_insn "*fms<mode>4_fpr" (define_insn "*fms<mode>4_fpr"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>") [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa")
(fma:SFDF (fma:SFDF
(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>,<Fv2>") (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa,wa")
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0") (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0")
(neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>"))))] (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa"))))]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"@ "@
fmsub<Ftrad> %0,%1,%2,%3 fmsub<Ftrad> %0,%1,%2,%3
...@@ -13445,12 +13440,12 @@ ...@@ -13445,12 +13440,12 @@
"") "")
(define_insn "*nfma<mode>4_fpr" (define_insn "*nfma<mode>4_fpr"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>") [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa")
(neg:SFDF (neg:SFDF
(fma:SFDF (fma:SFDF
(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>,<Fv2>") (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa,wa")
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0") (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0")
(match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>"))))] (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa"))))]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"@ "@
fnmadd<Ftrad> %0,%1,%2,%3 fnmadd<Ftrad> %0,%1,%2,%3
...@@ -13471,13 +13466,13 @@ ...@@ -13471,13 +13466,13 @@
"") "")
(define_insn "*nfmssf4_fpr" (define_insn "*nfmssf4_fpr"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>") [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa")
(neg:SFDF (neg:SFDF
(fma:SFDF (fma:SFDF
(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>,<Fv2>") (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa,wa")
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0") (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0")
(neg:SFDF (neg:SFDF
(match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>")))))] (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa")))))]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"@ "@
fnmsub<Ftrad> %0,%1,%2,%3 fnmsub<Ftrad> %0,%1,%2,%3
......
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