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riscv-gcc-1
Commit 1508cc46 by Nathan Sidwell Committed by Nathan Sidwell
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Add ms2 support 

	Add ms2 support
	* config/ms1/ms1.md (UNSPEC_BLOCKAGE, UNSPEC_EI, UNSPEC_DI): New
	constants.
	(call,load,store): New insn types.
	(mem_access, branch_access): Adjust reservation conditions.
	(define_delay): Adjust condition.
	(decrement_and_branch_until_zero): Allow for ms2.  Set branch
	type.
	(*decrement_and_rbanch_until_zero_no_clobber): Allow for ms2.
	(*movqi_internal,*movsi_internal,*movsf_internal): Use load,store
	insn type.
	(call_internal, call_value_internal, return_internal,
	return_interrupt_internal, eh_return_internal, indirect_jump,
	tablejump): Set call insn type.
	(blockage, ei, di): Use appropriate unspec const.
	* config/ms1/ms1.c (ms1_flag_delayed_branch): New.
	(ms1_get_attr_type): Adjust to give load & store types.
	(ms1_final_prescan_insn): Adjust for new insn types.  Don't look
	backwards past a barrier.
	(ms1_override_options): Accept ms2 arch.  Copy and reset delayed
	branch scheduling.
	(struct branch_info, struct label_info): New.
	(ms1_labels): New.
	(ms1_add_branches, ms1_check_delay_slot, ms1_reorg_hazard): New.
	(ms1_machine_reorg): New.
	(TARGET_MACHINE_DEPENDENT_REORG): Override.
	* config/ms1/crtn.asm: Add nop for ms2 JAL hazard.
	* config/ms1/ms1.h (processor_type): Add PROCESSOR_MS2.
	(ASM_SPEC, LIB_SPEC, STARTFILE_SPEC, ENDFILE_SPEC): Add ms2.
	(TARGET_MS2): New.

From-SVN: r106680
parent 456b8ce5
Showing with 81 additions and 27 deletions
gcc/ChangeLog
2005-11-09 Nathan Sidwell <nathan@codesourcery.com>
Add ms2 support
* config/ms1/ms1.md (UNSPEC_BLOCKAGE, UNSPEC_EI, UNSPEC_DI): New
constants.
(call,load,store): New insn types.
(mem_access, branch_access): Adjust reservation conditions.
(define_delay): Adjust condition.
(decrement_and_branch_until_zero): Allow for ms2. Set branch
type.
(*decrement_and_rbanch_until_zero_no_clobber): Allow for ms2.
(*movqi_internal,*movsi_internal,*movsf_internal): Use load,store
insn type.
(call_internal, call_value_internal, return_internal,
return_interrupt_internal, eh_return_internal, indirect_jump,
tablejump): Set call insn type.
(blockage, ei, di): Use appropriate unspec const.
* config/ms1/ms1.c (ms1_flag_delayed_branch): New.
(ms1_get_attr_type): Adjust to give load & store types.
(ms1_final_prescan_insn): Adjust for new insn types. Don't look
backwards past a barrier.
(ms1_override_options): Accept ms2 arch. Copy and reset delayed
branch scheduling.
(struct branch_info, struct label_info): New.
(ms1_labels): New.
(ms1_add_branches, ms1_check_delay_slot, ms1_reorg_hazard): New.
(ms1_machine_reorg): New.
(TARGET_MACHINE_DEPENDENT_REORG): Override.
* config/ms1/crtn.asm: Add nop for ms2 JAL hazard.
* config/ms1/ms1.h (processor_type): Add PROCESSOR_MS2.
(ASM_SPEC, LIB_SPEC, STARTFILE_SPEC, ENDFILE_SPEC): Add ms2.
(TARGET_MS2): New.
2005-11-09 Per Bothner <per@bothner.com>
Uros Bizjak <uros@kss-loka.si>
......
gcc/config/ms1/crtn.asm
......@@ -42,6 +42,7 @@
.align 4
ldw r14, sp, #0
addi sp, sp, #4
nop
jal r0, r14
or r0, r0, r0
......@@ -50,5 +51,6 @@
ldw r14, sp, #0
addi sp, sp, #4
nop
jal r0, r14
or r0, r0, r0
gcc/config/ms1/ms1.h
......@@ -25,7 +25,8 @@ enum processor_type
{
PROCESSOR_MS1_64_001,
PROCESSOR_MS1_16_002,
PROCESSOR_MS1_16_003
PROCESSOR_MS1_16_003,
PROCESSOR_MS2
};
enum epilogue_type
......@@ -40,7 +41,7 @@ extern enum processor_type ms1_cpu;
/* A C string constant that tells the GCC driver program options to pass to
the assembler. */
#undef ASM_SPEC
#define ASM_SPEC "%{march=ms1-16-002: -march=ms1-16-002} %{march=ms1-16-003: -march=ms1-16-003} %{!march=*: -march=ms1-16-002}"
#define ASM_SPEC "%{march=ms1-16-002: -march=ms1-16-002} %{march=ms1-16-003: -march=ms1-16-003} %{march=ms2: -march=ms2} %{!march=*: -march=ms1-16-002}"
/* A string to pass to at the end of the command given to the linker. */
#undef LIB_SPEC
......@@ -51,7 +52,9 @@ march=MS1-64-001:-T 64-001.ld%s; \
march=ms1-16-002:-T 16-002.ld%s; \
march=MS1-16-002:-T 16-002.ld%s; \
march=ms1-16-003:-T 16-003.ld%s; \
march=MS1-16-003:-T 16-003.ld%s}"
march=MS1-16-003:-T 16-003.ld%s; \
march=ms2:-T ms2.ld%s; \
march=MS2:-T ms2.ld%s}"
/* A string to pass at the very beginning of the command given to the
linker. */
......@@ -62,7 +65,9 @@ march=MS1-64-001:%{!mno-crt0:crt0-64-001.o%s} startup-64-001.o%s; \
march=ms1-16-002:%{!mno-crt0:crt0-16-002.o%s} startup-16-002.o%s; \
march=MS1-16-002:%{!mno-crt0:crt0-16-002.o%s} startup-16-002.o%s; \
march=ms1-16-003:%{!mno-crt0:crt0-16-003.o%s} startup-16-003.o%s; \
march=MS1-16-003:%{!mno-crt0:crt0-16-003.o%s} startup-16-003.o%s} \
march=MS1-16-003:%{!mno-crt0:crt0-16-003.o%s} startup-16-003.o%s; \
march=ms2:%{!mno-crt0:crt0-ms2.o%s} startup-ms2.o%s; \
march=MS2:%{!mno-crt0:crt0-ms2.o%s} startup-ms2.o%s} \
crti.o%s crtbegin.o%s"
/* A string to pass at the end of the command given to the linker. */
......@@ -73,7 +78,9 @@ march=MS1-64-001:exit-64-001.o%s; \
march=ms1-16-002:exit-16-002.o%s; \
march=MS1-16-002:exit-16-002.o%s; \
march=ms1-16-003:exit-16-003.o%s; \
march=MS1-16-003:exit-16-003.o%s} \
march=MS1-16-003:exit-16-003.o%s; \
march=ms2:exit-ms2.o%s; \
march=MS2:exit-ms2.o%s} \
crtend.o%s crtn.o%s"
/* Run-time target specifications. */
......@@ -89,6 +96,7 @@ march=MS1-16-003:exit-16-003.o%s} \
#define TARGET_MS1_64_001 (ms1_cpu == PROCESSOR_MS1_64_001)
#define TARGET_MS1_16_002 (ms1_cpu == PROCESSOR_MS1_16_002)
#define TARGET_MS1_16_003 (ms1_cpu == PROCESSOR_MS1_16_003)
#define TARGET_MS2 (ms1_cpu == PROCESSOR_MS2)
#define TARGET_VERSION fprintf (stderr, " (ms1)");
......
gcc/config/ms1/ms1.md
......@@ -19,8 +19,16 @@
;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
;; 02110-1301, USA.
;; UNSPECs
(define_constants
[
(UNSPEC_BLOCKAGE 0)
(UNSPEC_EI 1)
(UNSPEC_DI 2)
])
;; Attributes
(define_attr "type" "branch,mem,io,arith,complex,unknown"
(define_attr "type" "branch,call,load,store,io,arith,complex,unknown"
(const_string "unknown") )
;; If the attribute takes numeric values, no `enum' type will be defined and
......@@ -36,7 +44,7 @@
(define_cpu_unit "branch_unit" "other")
(define_insn_reservation "mem_access" 2
(eq_attr "type" "mem")
(ior (eq_attr "type" "load") (eq_attr "type" "store"))
"decode_unit+memory_unit*2")
(define_insn_reservation "io_access" 2
......@@ -44,7 +52,8 @@
"decode_unit+memory_unit*2")
(define_insn_reservation "branch_access" 2
(eq_attr "type" "branch")
(ior (eq_attr "type" "branch")
(eq_attr "type" "call"))
"decode_unit+branch_unit*2")
(define_insn_reservation "arith_access" 1
......@@ -64,7 +73,8 @@
;; the destination of the branch. Thus, only type that will be acceptable
;; (safe) is the arith type.
(define_delay (eq_attr "type" "branch")
(define_delay (ior (eq_attr "type" "branch")
(eq_attr "type" "call"))
[(eq_attr "type" "arith") (nil) (nil)])
......@@ -79,7 +89,7 @@
(plus:SI (match_dup 0)
(const_int -1)))
(clobber (match_scratch:SI 2 "=X,r"))]
"TARGET_MS1_16_003"
"TARGET_MS1_16_003 || TARGET_MS2"
"@
dbnz\t%0, %l1%#
#"
......@@ -98,9 +108,10 @@
(set (match_dup 0)
(plus:SI (match_dup 0)
(const_int -1)))]
"TARGET_MS1_16_003"
"TARGET_MS1_16_003 || TARGET_MS2"
"dbnz\t%0, %l1%#"
[(set_attr "length" "4")]
[(set_attr "length" "4")
(set_attr "type" "branch")]
)
;; Split the above to handle the case where operand 0 is in memory
......@@ -116,7 +127,7 @@
(plus:SI (match_dup 0)
(const_int -1)))
(clobber (match_scratch:SI 2 ""))]
"TARGET_MS1_16_003"
"TARGET_MS1_16_003 || TARGET_MS2"
[(set (match_dup 2) (match_dup 0))
(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
(set (match_dup 0) (match_dup 2))
......@@ -143,7 +154,7 @@
(label_ref (match_operand 2 "" ""))
(pc)))
]
"TARGET_MS1_16_003"
"TARGET_MS1_16_003 || TARGET_MS2"
[(parallel [(set (pc)
(if_then_else
(ne (match_dup 0) (const_int 0))
......@@ -308,7 +319,7 @@
stb %1, %0
addi %0, r0, %1"
[(set_attr "length" "4,4,4,4")
(set_attr "type" "arith,mem,mem,arith")])
(set_attr "type" "arith,load,store,arith")])
(define_insn "*movqi_internal_nobyte"
[(set (match_operand:QI 0 "register_operand" "=r,r")
......@@ -566,7 +577,7 @@
nori %0, r0, %N1
ldui %0, %H1\;addui %0, %0, %L1"
[(set_attr "length" "4,4,4,4,4,4,4,8")
(set_attr "type" "arith,mem,mem,arith,arith,arith,arith,complex")]
(set_attr "type" "arith,load,store,arith,arith,arith,arith,complex")]
)
;; Floating Point Moves
......@@ -641,7 +652,7 @@
ldw %0, %1
stw %1, %0"
[(set_attr "length" "4,4,4")
(set_attr "type" "arith,mem,mem")]
(set_attr "type" "arith,load,store")]
)
(define_expand "movdf"
......@@ -1269,7 +1280,7 @@
""
"jal r14, %0%#"
[(set_attr "length" "4")
(set_attr "type" "branch")])
(set_attr "type" "call")])
(define_expand "call_value"
[(parallel [(set (match_operand 0 "register_operand" "")
......@@ -1292,7 +1303,7 @@
""
"jal r14, %1%#"
[(set_attr "length" "4")
(set_attr "type" "branch")])
(set_attr "type" "call")])
;; Subroutine return
(define_insn "return_internal"
......@@ -1302,7 +1313,7 @@
""
"jal r0, r14%#"
[(set_attr "length" "4")
(set_attr "type" "branch")])
(set_attr "type" "call")])
;; Interrupt return
(define_insn "return_interrupt_internal"
......@@ -1312,7 +1323,7 @@
""
"reti r15%#"
[(set_attr "length" "4")
(set_attr "type" "branch")])
(set_attr "type" "call")])
;; Subroutine return
(define_insn "eh_return_internal"
......@@ -1324,7 +1335,7 @@
""
"jal r0, r11%#"
[(set_attr "length" "4")
(set_attr "type" "branch")])
(set_attr "type" "call")])
;; Normal unconditional jump
......@@ -1341,7 +1352,7 @@
""
"jal r0,%0%#"
[(set_attr "length" "4")
(set_attr "type" "branch")])
(set_attr "type" "call")])
(define_insn "tablejump"
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
......@@ -1349,7 +1360,7 @@
""
"jal r0, %0%#"
[(set_attr "length" "4")
(set_attr "type" "branch")])
(set_attr "type" "call")])
(define_expand "prologue"
......@@ -1412,7 +1423,7 @@
;; Pseudo instruction that prevents the scheduler from moving code above this
;; point.
(define_insn "blockage"
[(unspec_volatile [(const_int 0)] 0)]
[(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
""
""
[(set_attr "length" "0")])
......@@ -1442,14 +1453,14 @@
;; Enable interrupts template
(define_insn "ei"
[(unspec_volatile [(const_int 0)] 1)]
[(unspec_volatile [(const_int 0)] UNSPEC_EI)]
""
"ei"
[(set_attr "length" "4")])
;; Enable interrupts template
(define_insn "di"
[(unspec_volatile [(const_int 0)] 2)]
[(unspec_volatile [(const_int 0)] UNSPEC_DI)]
""
"di"
[(set_attr "length" "4")])
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