For attribute named "type", subdivide "alu" into "alu_reg" and "simple_alu_imm".

Set type attribute as appropriate in RTL patterns with immediate operands.
Update pipeline descriptions to use the new values of type attribute.

gcc/

2012-11-30  Ramana Radhakrishnan <Ramana.Radhakrishnan@arm.com>
            Greta Yorsh  <Greta.Yorsh@arm.com>

        * config/arm/arm.md (type): Subdivide "alu" into "alu_reg"
        and "simple_alu_imm".
        (core_cycles): Use new names.
        (arm_addsi3): Set type of patterns to use to alu_reg and simple_alu_imm.
        (addsi3_compare0, addsi3_compare0_scratch): Likewise.
        (addsi3_compare_op1, addsi3_compare_op2, compare_addsi2_op0): Likewise.
        (compare_addsi2_op1, arm_subsi3_insn, subsi3_compare0): Likewise.
        (subsi3_compare, arm_decscc,arm_andsi3_insn): Likewise.
        (thumb1_andsi3_insn, andsi3_compare0_scratch): Likewise.
        (zeroextractsi_compare0_scratch,iorsi3_insn,iorsi3_compare0): Likewise.
        (iorsi3_compare0_scratch, arm_xorsi3, thumb1_xorsi3_insn): Likewise.
        (xorsi3_compare0, xorsi3_compare0_scratch): Likewise.
        (thumb1_zero_extendhisi2,arm_zero_extendhisi2_v6): Likewise.
        (thumb1_zero_extendqisi2_v, arm_zero_extendqisi2_v6): Likewise.
	(thumb1_extendhisi2, arm_extendqisi_v6): Likewise.
	(thumb1_extendqisi2, arm_movsi_insn): Likewise.
        (movsi_compare0, movhi_insn_arch4, movhi_bytes): Likewise.
        (arm_movqi_insn, thumb1_movqi_insn, arm_cmpsi_insn): Likewise.
        (movsicc_insn, if_plus_move, if_move_plus): Likewise.
        * config/arm/neon.md (neon_mov<mode>/VDX): Likewise.
        (neon_mov<mode>/VQXMOV): Likewise.
        * config/arm/arm1020e.md (1020alu_op): Likewise.
        * config/arm/fmp626.md (mp626_alu_op): Likewise.
        * config/arm/fa726te.md (726te_alu_op): Likewise.
        * config/arm/fa626te.md (626te_alu_op): Likewise.
        * config/arm/fa606te.md (606te_alu_op): Likewise.
        * config/arm/fa526.md (526_alu_op): Likewise.
        * config/arm/cortex-r4.md (cortex_r4_alu, cortex_r4_mov): Likewise.
        * config/arm/cortex-m4.md (cortex_m4_alu): Likewise.
        * config/arm/cortex-a9.md (cprtex_a9_dp): Likewise.
        * config/arm/cortex-a8.md (cortex_a8_alu, cortex_a8_mov): Likewise.
        * config/arm/cortex-a5.md (cortex_a5_alu): Likewise.
        * config/arm/cortex-a15.md (cortex_a15_alu): Likewise.
        * config/arm/arm926ejs.md (9_alu_op): Likewise.
        * config/arm/arm1136jfs.md (11_alu_op): Likewise.
        * config/arm/arm1026ejs.md (alu_op): Likewise.


Co-Authored-By: Greta Yorsh <greta.yorsh@arm.com>

From-SVN: r193996

gcc/ChangeLog

+2012-11-30  Ramana Radhakrishnan <Ramana.Radhakrishnan@arm.com>
+            Greta Yorsh  <Greta.Yorsh@arm.com>
+
+        * config/arm/arm.md (type): Subdivide "alu" into "alu_reg"
+        and "simple_alu_imm".
+        (core_cycles): Use new names.
+        (arm_addsi3): Set type of patterns to use to alu_reg and simple_alu_imm.
+        (addsi3_compare0, addsi3_compare0_scratch): Likewise.
+        (addsi3_compare_op1, addsi3_compare_op2, compare_addsi2_op0): Likewise.
+        (compare_addsi2_op1, arm_subsi3_insn, subsi3_compare0): Likewise.
+        (subsi3_compare, arm_decscc,arm_andsi3_insn): Likewise.
+        (thumb1_andsi3_insn, andsi3_compare0_scratch): Likewise.
+        (zeroextractsi_compare0_scratch,iorsi3_insn,iorsi3_compare0): Likewise.
+        (iorsi3_compare0_scratch, arm_xorsi3, thumb1_xorsi3_insn): Likewise.
+        (xorsi3_compare0, xorsi3_compare0_scratch): Likewise.
+        (thumb1_zero_extendhisi2,arm_zero_extendhisi2_v6): Likewise.
+        (thumb1_zero_extendqisi2_v, arm_zero_extendqisi2_v6): Likewise.
+	(thumb1_extendhisi2, arm_extendqisi_v6): Likewise.
+	(thumb1_extendqisi2, arm_movsi_insn): Likewise.
+        (movsi_compare0, movhi_insn_arch4, movhi_bytes): Likewise.
+        (arm_movqi_insn, thumb1_movqi_insn, arm_cmpsi_insn): Likewise.
+        (movsicc_insn, if_plus_move, if_move_plus): Likewise.
+        * config/arm/neon.md (neon_mov<mode>/VDX): Likewise.
+        (neon_mov<mode>/VQXMOV): Likewise.
+        * config/arm/arm1020e.md (1020alu_op): Likewise.
+        * config/arm/fmp626.md (mp626_alu_op): Likewise.
+        * config/arm/fa726te.md (726te_alu_op): Likewise.
+        * config/arm/fa626te.md (626te_alu_op): Likewise.
+        * config/arm/fa606te.md (606te_alu_op): Likewise.
+        * config/arm/fa526.md (526_alu_op): Likewise.
+        * config/arm/cortex-r4.md (cortex_r4_alu, cortex_r4_mov): Likewise.
+        * config/arm/cortex-m4.md (cortex_m4_alu): Likewise.
+        * config/arm/cortex-a9.md (cprtex_a9_dp): Likewise.
+        * config/arm/cortex-a8.md (cortex_a8_alu, cortex_a8_mov): Likewise.
+        * config/arm/cortex-a5.md (cortex_a5_alu): Likewise.
+        * config/arm/cortex-a15.md (cortex_a15_alu): Likewise.
+        * config/arm/arm926ejs.md (9_alu_op): Likewise.
+        * config/arm/arm1136jfs.md (11_alu_op): Likewise.
+        * config/arm/arm1026ejs.md (alu_op): Likewise.
+
 2012-11-30  Richard Biener  <rguenther@suse.de>
 
 	* tree-ssa-pre.c (get_expr_value_id): Do not allocate value-ids

gcc/config/arm/arm1020e.md

@@ -66,7 +66,7 @@
 ;; ALU operations with no shifted operand
 (define_insn_reservation "1020alu_op" 1 
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "type" "alu"))
+      (eq_attr "type" "alu_reg,simple_alu_imm"))
  "1020a_e,1020a_m,1020a_w")
 
 ;; ALU operations with a shift-by-constant operand

gcc/config/arm/arm1026ejs.md

@@ -66,7 +66,7 @@
 ;; ALU operations with no shifted operand
 (define_insn_reservation "alu_op" 1 
  (and (eq_attr "tune" "arm1026ejs")
-      (eq_attr "type" "alu"))
+      (eq_attr "type" "alu_reg,simple_alu_imm"))
  "a_e,a_m,a_w")
 
 ;; ALU operations with a shift-by-constant operand

gcc/config/arm/arm1136jfs.md

@@ -75,7 +75,7 @@
 ;; ALU operations with no shifted operand
 (define_insn_reservation "11_alu_op" 2
  (and (eq_attr "tune" "arm1136js,arm1136jfs")
-      (eq_attr "type" "alu"))
+      (eq_attr "type" "alu_reg,simple_alu_imm"))
  "e_1,e_2,e_3,e_wb")
 
 ;; ALU operations with a shift-by-constant operand

gcc/config/arm/arm926ejs.md

@@ -58,7 +58,7 @@
 ;; ALU operations with no shifted operand
 (define_insn_reservation "9_alu_op" 1 
  (and (eq_attr "tune" "arm926ejs")
-      (eq_attr "type" "alu,alu_shift"))
+      (eq_attr "type" "alu_reg,simple_alu_imm,alu_shift"))
  "e,m,w")
 
 ;; ALU operations with a shift-by-register operand

gcc/config/arm/cortex-a15.md

@@ -61,7 +61,7 @@
 ;; Simple ALU without shift
 (define_insn_reservation "cortex_a15_alu" 2
   (and (eq_attr "tune" "cortexa15")
-       (and (eq_attr "type" "alu")
+       (and (eq_attr "type" "alu_reg,simple_alu_imm")
             (eq_attr "neon_type" "none")))
   "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
 

gcc/config/arm/cortex-a5.md

@@ -58,7 +58,7 @@
 
 (define_insn_reservation "cortex_a5_alu" 2
   (and (eq_attr "tune" "cortexa5")
-       (eq_attr "type" "alu"))
+       (eq_attr "type" "alu_reg,simple_alu_imm"))
   "cortex_a5_ex1")
 
 (define_insn_reservation "cortex_a5_alu_shift" 2

gcc/config/arm/cortex-a8.md

@@ -85,7 +85,7 @@
 ;; (source read in E2 and destination available at the end of that cycle).
 (define_insn_reservation "cortex_a8_alu" 2
   (and (eq_attr "tune" "cortexa8")
-       (ior (and (and (eq_attr "type" "alu")
+       (ior (and (and (eq_attr "type" "alu_reg,simple_alu_imm")
 		      (eq_attr "neon_type" "none"))
 		 (not (eq_attr "insn" "mov,mvn")))
             (eq_attr "insn" "clz")))
@@ -107,7 +107,7 @@
 
 (define_insn_reservation "cortex_a8_mov" 1
   (and (eq_attr "tune" "cortexa8")
-       (and (eq_attr "type" "alu,alu_shift,alu_shift_reg")
+       (and (eq_attr "type" "alu_reg,simple_alu_imm,alu_shift,alu_shift_reg")
             (eq_attr "insn" "mov,mvn")))
   "cortex_a8_default")
 

gcc/config/arm/cortex-a9.md

@@ -80,7 +80,7 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
 ;; which can go down E2 without any problem.
 (define_insn_reservation "cortex_a9_dp" 2
   (and (eq_attr "tune" "cortexa9")
-         (ior (and (eq_attr "type" "alu")
+         (ior (and (eq_attr "type" "alu_reg,simple_alu_imm")
                         (eq_attr "neon_type" "none"))
 	      (and (and (eq_attr "type" "alu_shift_reg, alu_shift")
 			(eq_attr "insn" "mov"))

gcc/config/arm/cortex-m4.md

@@ -31,7 +31,7 @@
 ;; ALU and multiply is one cycle.
 (define_insn_reservation "cortex_m4_alu" 1
   (and (eq_attr "tune" "cortexm4")
-       (eq_attr "type" "alu,alu_shift,alu_shift_reg,mult"))
+       (eq_attr "type" "alu_reg,simple_alu_imm,alu_shift,alu_shift_reg,mult"))
   "cortex_m4_ex")
 
 ;; Byte, half-word and word load is two cycles.

gcc/config/arm/cortex-r4.md

@@ -78,13 +78,13 @@
 ;; for the purposes of the dual-issue constraints above.
 (define_insn_reservation "cortex_r4_alu" 2
   (and (eq_attr "tune_cortexr4" "yes")
-       (and (eq_attr "type" "alu")
+       (and (eq_attr "type" "alu_reg,simple_alu_imm")
             (not (eq_attr "insn" "mov"))))
   "cortex_r4_alu")
 
 (define_insn_reservation "cortex_r4_mov" 2
   (and (eq_attr "tune_cortexr4" "yes")
-       (and (eq_attr "type" "alu")
+       (and (eq_attr "type" "alu_reg,simple_alu_imm")
             (eq_attr "insn" "mov")))
   "cortex_r4_mov")
 

gcc/config/arm/fa526.md

@@ -62,7 +62,7 @@
 ;; ALU operations
 (define_insn_reservation "526_alu_op" 1
  (and (eq_attr "tune" "fa526")
-      (eq_attr "type" "alu"))
+      (eq_attr "type" "alu_reg,simple_alu_imm"))
  "fa526_core")
 
 (define_insn_reservation "526_alu_shift_op" 2

gcc/config/arm/fa606te.md

@@ -62,7 +62,7 @@
 ;; ALU operations
 (define_insn_reservation "606te_alu_op" 1
  (and (eq_attr "tune" "fa606te")
-      (eq_attr "type" "alu,alu_shift,alu_shift_reg"))
+      (eq_attr "type" "alu_reg,simple_alu_imm,alu_shift,alu_shift_reg"))
  "fa606te_core")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

gcc/config/arm/fa626te.md

@@ -68,7 +68,7 @@
 ;; ALU operations
 (define_insn_reservation "626te_alu_op" 1
  (and (eq_attr "tune" "fa626,fa626te")
-      (eq_attr "type" "alu"))
+      (eq_attr "type" "alu_reg,simple_alu_imm"))
  "fa626te_core")
 
 (define_insn_reservation "626te_alu_shift_op" 2

gcc/config/arm/fa726te.md

@@ -85,7 +85,7 @@
 ;; Other ALU instructions 2 cycles.
 (define_insn_reservation "726te_alu_op" 1
  (and (eq_attr "tune" "fa726te")
-      (and (eq_attr "type" "alu")
+      (and (eq_attr "type" "alu_reg,simple_alu_imm")
            (not (eq_attr "insn" "mov,mvn"))))
   "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
 

gcc/config/arm/fmp626.md

@@ -63,7 +63,7 @@
 ;; ALU operations
 (define_insn_reservation "mp626_alu_op" 1
  (and (eq_attr "tune" "fmp626")
-      (eq_attr "type" "alu"))
+      (eq_attr "type" "alu_reg,simple_alu_imm"))
  "fmp626_core")
 
 (define_insn_reservation "mp626_alu_shift_op" 2

gcc/config/arm/neon.md

@@ -193,7 +193,7 @@
     }
 }
  [(set_attr "neon_type" "neon_int_1,*,neon_vmov,*,neon_mrrc,neon_mcr_2_mcrr,*,*,*")
-  (set_attr "type" "*,f_stored,*,f_loadd,*,*,alu,load2,store2")
+  (set_attr "type" "*,f_stored,*,f_loadd,*,*,alu_reg,load2,store2")
   (set_attr "insn" "*,*,*,*,*,*,mov,*,*")
   (set_attr "length" "4,4,4,4,4,4,8,8,8")
   (set_attr "arm_pool_range"     "*,*,*,1020,*,*,*,1020,*")
@@ -239,7 +239,7 @@
 }
   [(set_attr "neon_type" "neon_int_1,neon_stm_2,neon_vmov,neon_ldm_2,\
                           neon_mrrc,neon_mcr_2_mcrr,*,*,*")
-   (set_attr "type" "*,*,*,*,*,*,alu,load4,store4")
+   (set_attr "type" "*,*,*,*,*,*,alu_reg,load4,store4")
    (set_attr "insn" "*,*,*,*,*,*,mov,*,*")
    (set_attr "length" "4,8,4,8,8,8,16,8,16")
    (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*")

gcc/config/arm/thumb2.md

 ;; ARM Thumb-2 Machine Description
-;; Copyright (C) 2007, 2008, 2010 Free Software Foundation, Inc.
+;; Copyright (C) 2007, 2008, 2010, 2012 Free Software Foundation, Inc.
 ;; Written by CodeSourcery, LLC.
 ;;
 ;; This file is part of GCC.
@@ -180,7 +180,7 @@
    ldr%?\\t%0, %1
    str%?\\t%1, %0
    str%?\\t%1, %0"
-  [(set_attr "type" "*,*,*,*,load1,load1,store1,store1")
+  [(set_attr "type" "*,*,simple_alu_imm,*,load1,load1,store1,store1")
    (set_attr "predicable" "yes")
    (set_attr "pool_range" "*,*,*,*,1018,4094,*,*")
    (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")]
@@ -568,7 +568,11 @@
   "@
    sxtb%?\\t%0, %1
    ldr%(sb%)\\t%0, %1"
-  [(set_attr "type" "alu_shift,load_byte")
+  [(set_attr_alternative "type"
+                         [(if_then_else (eq_attr "tune" "cortexa7")
+                                        (const_string "simple_alu_imm")
+                                        (const_string "alu_shift"))
+                          (const_string "load_byte")])
    (set_attr "predicable" "yes")
    (set_attr "pool_range" "*,4094")
    (set_attr "neg_pool_range" "*,250")]
@@ -581,7 +585,11 @@
   "@
    uxth%?\\t%0, %1
    ldr%(h%)\\t%0, %1"
-  [(set_attr "type" "alu_shift,load_byte")
+  [(set_attr_alternative "type"
+                         [(if_then_else (eq_attr "tune" "cortexa7")
+                                        (const_string "simple_alu_imm")
+                                        (const_string "alu_shift"))
+                          (const_string "load_byte")])
    (set_attr "predicable" "yes")
    (set_attr "pool_range" "*,4094")
    (set_attr "neg_pool_range" "*,250")]
@@ -594,7 +602,11 @@
   "@
    uxtb%(%)\\t%0, %1
    ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
-  [(set_attr "type" "alu_shift,load_byte")
+  [(set_attr_alternative "type"
+                         [(if_then_else (eq_attr "tune" "cortexa7")
+                                        (const_string "simple_alu_imm")
+                                        (const_string "alu_shift"))
+                          (const_string "load_byte")])
    (set_attr "predicable" "yes")
    (set_attr "pool_range" "*,4094")
    (set_attr "neg_pool_range" "*,250")]
@@ -790,8 +802,8 @@
 (define_insn "*thumb2_addsi3_compare0_scratch"
   [(set (reg:CC_NOOV CC_REGNUM)
 	(compare:CC_NOOV
-	  (plus:SI (match_operand:SI 0 "s_register_operand" "l,  r")
-		   (match_operand:SI 1 "arm_add_operand"    "lPv,rIL"))
+	  (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,  r,r")
+		   (match_operand:SI 1 "arm_add_operand"    "Pv,l,IL,r"))
 	  (const_int 0)))]
   "TARGET_THUMB2"
   "*
@@ -808,7 +820,8 @@
       return \"cmn\\t%0, %1\";
   "
   [(set_attr "conds" "set")
-   (set_attr "length" "2,4")]
+   (set_attr "length" "2,2,4,4")
+   (set_attr "type"   "simple_alu_imm,*,simple_alu_imm,*")]
 )
 
 (define_insn "*thumb2_mulsi_short"

gcc/config/arm/vfp.md

@@ -77,7 +77,7 @@
     }
   "
   [(set_attr "predicable" "yes")
-   (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
+   (set_attr "type" "*,*,simple_alu_imm,simple_alu_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
    (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
    (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*")
    (set_attr "pool_range"     "*,*,*,*,4096,*,*,*,*,1020,*")