Commit 13a7eb33 by Jim Wilson

(umulsidi3): Use uns_arith_operand not arith_operand.

(const_umulsidi3): Use uns_small_int not small_int.
(ashlsi3+1, ashlsi3+2): New patterns to replace shift
and compare with addcc.

From-SVN: r5628
parent 922bd191
...@@ -1840,7 +1840,7 @@ ...@@ -1840,7 +1840,7 @@
(define_expand "umulsidi3" (define_expand "umulsidi3"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
(zero_extend:DI (match_operand:SI 2 "arith_operand" ""))))] (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" ""))))]
"TARGET_V8 || TARGET_SPARCLITE" "TARGET_V8 || TARGET_SPARCLITE"
" "
{ {
...@@ -1864,7 +1864,7 @@ ...@@ -1864,7 +1864,7 @@
(define_insn "const_umulsidi3" (define_insn "const_umulsidi3"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
(match_operand:SI 2 "small_int" "I")))] (match_operand:SI 2 "uns_small_int" "")))]
"TARGET_V8 || TARGET_SPARCLITE" "TARGET_V8 || TARGET_SPARCLITE"
"umul %1,%2,%R0\;rd %%y,%0" "umul %1,%2,%R0\;rd %%y,%0"
[(set_attr "length" "2")]) [(set_attr "length" "2")])
...@@ -2529,6 +2529,25 @@ ...@@ -2529,6 +2529,25 @@
"" ""
"sll %1,%2,%0") "sll %1,%2,%0")
(define_insn ""
[(set (reg:CC_NOOV 0)
(compare:CC_NOOV (ashift:SI (match_operand:SI 0 "register_operand" "r")
(const_int 1))
(const_int 0)))]
""
"addcc %0,%0,%%g0"
[(set_attr "type" "compare")])
(define_insn ""
[(set (reg:CC_NOOV 0)
(compare:CC_NOOV (ashift:SI (match_operand:SI 1 "register_operand" "r")
(const_int 1))
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=r")
(ashift:SI (match_dup 1) (const_int 1)))]
""
"addcc %1,%1,%0")
(define_insn "ashrsi3" (define_insn "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "r") (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
......
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