AVX-512. Fix mem operand modifier for Intel syntax.

PR target/70662
gcc/
	* config/i386/sse.md: Use proper memory operand
	modifiers.
testsuite/gcc/
	* gcc.target/i386/pr70662.c: New test.

From-SVN: r235008

gcc/ChangeLog

+2016-04-15  Kirill Yukhin  <kirill.yukhin@intel.com>
+
+	PR target/70662
+	* config/i386/sse.md: Use proper memory operand
+	modifiers.
+
+
 2016-04-15  Richard Biener  <rguenther@suse.de>
 	Alan Modra  <amodra@gmail.com>
 

gcc/config/i386/sse.md

@@ -17262,9 +17262,12 @@
   /*  There is no DF broadcast (in AVX-512*) to 128b register.
       Mimic it with integer variant.  */
   if (<MODE>mode == V2DFmode)
-    return "vpbroadcastq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}";
+    return "vpbroadcastq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}";
+
+  if (GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) == 32)
+    return "v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %k1}";
   else
-    return "v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}";
+    return "v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}";
 }
   [(set_attr "type" "ssemov")
    (set_attr "prefix" "evex")

gcc/testsuite/ChangeLog

+2016-04-15  Kirill Yukhin  <kirill.yukhin@intel.com>
+
+	PR target/70662
+	* gcc.target/i386/pr70662.c: New test.
+
 2016-04-15  Richard Biener  <rguenther@suse.de>
 	Alan Modra  <amodra@gmail.com>
 

gcc/testsuite/gcc.target/i386/pr70662.c

+/* { dg-do assemble { target { ! ia32 } } } */
+/* { dg-require-effective-target avx512vbmi } */
+/* { dg-require-effective-target masm_intel } */
+/* { dg-options "-Og -fschedule-insns -fno-tree-fre -mavx512vbmi --param=max-sched-ready-insns=1 -masm=intel" } */
+
+typedef char v64u8 __attribute__((vector_size(64)));
+typedef int v64u32 __attribute__((vector_size(64)));
+typedef long v64u64 __attribute__((vector_size(64)));
+typedef __int128 v64u128 __attribute__((vector_size(64)));
+
+v64u128
+foo(int u8_0, unsigned u128_0, v64u32 v64u32_1, v64u32 v64u32_0, v64u64 v64u64_0, v64u128 v64u128_0)
+{
+  v64u8 v64u8_0 = v64u8_0;
+  v64u32_0 = v64u32_0 >> (v64u32){0, 0, 0, 1, 0, ((v64u64)v64u64_0)[u8_0], ((v64u32)v64u128_0)[15], 0, 0, 0, 0, 4, ((v64u64)v64u64_0)[v64u32_0[0]] - 1};
+  v64u8_0 = v64u8_0 << ((v64u8)v64u32_1 & 1);
+  v64u64_0[0] >>= 0;
+  return u128_0 + (v64u128)v64u8_0 + (v64u128)v64u32_0 + (v64u128)v64u64_0;
+}