Commit 1330f7d5 by Douglas B Rupp Committed by Douglas Rupp

alpha-protos.h: Update.

	* config/alpha/alpha-protos.h: Update.

	* config/alpha/alpha.c: (LINKAGE_SYMBOL_REF_P): New macro.
	(alpha_legitimate_address_p): Test LINKAGE_SYMBOL_REF_P.
	(alpha_linkage_symbol_p): New static function.
	(print_operand_address): Print linkage operand.

	(alpha_funcs_num, alpha_funcs_tree, alpha_links_tree): New static
	variables.
	(reloc_kind): New enum.
	(struct alpha_funcs): New struct.
	(struct alpha_links): Add reloc_kind field. Rename links_kind field.

	(alpha_need_linkage): Rewrite.
	(alpha_use_linkage): New global function.
	(alpha_write_linkage): Rewrite and make static.
	(alpha_write_one_linkage): Rewrite

	(alpha_start_function): Remove procedure descriptor output.
	(alpha_end_function): Write linkages at end of each function.

	* config/alpha/alpha.md (call_vms, call_value_vms): Rewrite.
	(call_vms_1, call_value_vms_1): Rewrite.

	* config/alpha/vms.h (ASM_FILE_END): Remove.

From-SVN: r56338
parent d1f1cc6a
2002-08-14 Douglas B Rupp <rupp@gnat.com>
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.c: (LINKAGE_SYMBOL_REF_P): New macro.
(alpha_legitimate_address_p): Test LINKAGE_SYMBOL_REF_P.
(alpha_linkage_symbol_p): New static function.
(print_operand_address): Print linkage operand.
(alpha_funcs_num, alpha_funcs_tree, alpha_links_tree): New static
variables.
(reloc_kind): New enum.
(struct alpha_funcs): New struct.
(struct alpha_links): Add reloc_kind field. Rename links_kind field.
(alpha_need_linkage): Rewrite.
(alpha_use_linkage): New global function.
(alpha_write_linkage): Rewrite and make static.
(alpha_write_one_linkage): Rewrite
(alpha_start_function): Remove procedure descriptor output.
(alpha_end_function): Write linkages at end of each function.
* config/alpha/alpha.md (call_vms, call_value_vms): Rewrite.
(call_vms_1, call_value_vms_1): Rewrite.
* config/alpha/vms.h (ASM_FILE_END): Remove.
2002-08-14 Richard Henderson <rth@redhat.com> 2002-08-14 Richard Henderson <rth@redhat.com>
* ggc-page.c (RTL_SIZE): New. * ggc-page.c (RTL_SIZE): New.
......
...@@ -159,13 +159,13 @@ extern void alpha_emit_xfloating_cvt PARAMS ((enum rtx_code, rtx[])); ...@@ -159,13 +159,13 @@ extern void alpha_emit_xfloating_cvt PARAMS ((enum rtx_code, rtx[]));
#endif #endif
extern rtx alpha_need_linkage PARAMS ((const char *, int)); extern rtx alpha_need_linkage PARAMS ((const char *, int));
extern rtx alpha_use_linkage PARAMS ((rtx, tree, int, int));
#if TARGET_ABI_OPEN_VMS #if TARGET_ABI_OPEN_VMS
#ifdef HAVE_MACHINE_MODES #ifdef HAVE_MACHINE_MODES
extern enum avms_arg_type alpha_arg_type PARAMS ((enum machine_mode)); extern enum avms_arg_type alpha_arg_type PARAMS ((enum machine_mode));
#endif #endif
extern rtx alpha_arg_info_reg_val PARAMS ((CUMULATIVE_ARGS)); extern rtx alpha_arg_info_reg_val PARAMS ((CUMULATIVE_ARGS));
extern void alpha_write_linkage PARAMS ((FILE *));
#endif /* TARGET_ABI_OPEN_VMS */ #endif /* TARGET_ABI_OPEN_VMS */
extern rtx unicosmk_add_call_info_word PARAMS ((rtx)); extern rtx unicosmk_add_call_info_word PARAMS ((rtx));
......
...@@ -4429,11 +4429,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" ...@@ -4429,11 +4429,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]); emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
if (GET_CODE (operands[0]) == SYMBOL_REF) if (GET_CODE (operands[0]) == SYMBOL_REF)
{ {
rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0); alpha_need_linkage (XSTR (operands[0], 0), 0);
emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage)); operands[2] = const0_rtx;
operands[2]
= validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
} }
else else
{ {
...@@ -4531,11 +4529,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" ...@@ -4531,11 +4529,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]); emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
if (GET_CODE (operands[1]) == SYMBOL_REF) if (GET_CODE (operands[1]) == SYMBOL_REF)
{ {
rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0); alpha_need_linkage (XSTR (operands[1], 0), 0);
emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage)); operands[3] = const0_rtx;
operands[3]
= validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
} }
else else
{ {
...@@ -4720,17 +4716,31 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" ...@@ -4720,17 +4716,31 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
[(set_attr "type" "jsr") [(set_attr "type" "jsr")
(set_attr "length" "*,*,12")]) (set_attr "length" "*,*,12")])
; GAS relies on the order and position of instructions output below in order
; to generate relocs for VMS link to potentially optimize the call.
; Please do not molest.
(define_insn "*call_vms_1" (define_insn "*call_vms_1"
[(call (mem:DI (match_operand:DI 0 "call_operand" "r,s")) [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
(match_operand 1 "" "")) (match_operand 1 "" ""))
(use (match_operand:DI 2 "nonimmediate_operand" "r,m")) (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
(use (reg:DI 25)) (use (reg:DI 25))
(use (reg:DI 26)) (use (reg:DI 26))
(clobber (reg:DI 27))] (clobber (reg:DI 27))]
"TARGET_ABI_OPEN_VMS" "TARGET_ABI_OPEN_VMS"
"@ "*
mov %2,$27\;jsr $26,0\;ldq $27,0($29) {
ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)" switch (which_alternative)
{
case 0:
return \"mov %2,$27\;jsr $26,0\;ldq $27,0($29)\";
case 1:
operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0);
operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0);
return \"ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)\";
default:
abort();
}
}"
[(set_attr "type" "jsr") [(set_attr "type" "jsr")
(set_attr "length" "12,16")]) (set_attr "length" "12,16")])
...@@ -7896,18 +7906,32 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" ...@@ -7896,18 +7906,32 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
[(set_attr "type" "jsr") [(set_attr "type" "jsr")
(set_attr "length" "*,*,12")]) (set_attr "length" "*,*,12")])
; GAS relies on the order and position of instructions output below in order
; to generate relocs for VMS link to potentially optimize the call.
; Please do not molest.
(define_insn "*call_value_vms_1" (define_insn "*call_value_vms_1"
[(set (match_operand 0 "" "") [(set (match_operand 0 "" "")
(call (mem:DI (match_operand:DI 1 "call_operand" "r,s")) (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
(match_operand 2 "" ""))) (match_operand 2 "" "")))
(use (match_operand:DI 3 "nonimmediate_operand" "r,m")) (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
(use (reg:DI 25)) (use (reg:DI 25))
(use (reg:DI 26)) (use (reg:DI 26))
(clobber (reg:DI 27))] (clobber (reg:DI 27))]
"TARGET_ABI_OPEN_VMS" "TARGET_ABI_OPEN_VMS"
"@ "*
mov %3,$27\;jsr $26,0\;ldq $27,0($29) {
ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)" switch (which_alternative)
{
case 0:
return \"mov %3,$27\;jsr $26,0\;ldq $27,0($29)\";
case 1:
operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0);
operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0);
return \"ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)\";
default:
abort();
}
}"
[(set_attr "type" "jsr") [(set_attr "type" "jsr")
(set_attr "length" "12,16")]) (set_attr "length" "12,16")])
......
...@@ -300,8 +300,6 @@ extern void literals_section PARAMS ((void)); ...@@ -300,8 +300,6 @@ extern void literals_section PARAMS ((void));
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
fprintf (FILE, "\t.quad $L%d\n", (VALUE)) fprintf (FILE, "\t.quad $L%d\n", (VALUE))
#define ASM_FILE_END(FILE) alpha_write_linkage (FILE);
#undef CASE_VECTOR_MODE #undef CASE_VECTOR_MODE
#define CASE_VECTOR_MODE DImode #define CASE_VECTOR_MODE DImode
#undef CASE_VECTOR_PC_RELATIVE #undef CASE_VECTOR_PC_RELATIVE
......
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