Commit 12dc6974 by Sofiane Naci Committed by Sofiane Naci

aarch64.md: New movtf split.

	* config/aarch64/aarch64.md: New movtf split.
	(*movtf_aarch64): Update.
	(aarch64_movdi_tilow): Handle TF modes and rename to
	aarch64_movdi_<mode>low.
	(aarch64_movdi_tihigh): Handle TF modes and rename to
	aarch64_movdi_<mode>high
	(aarch64_movtihigh_di): Handle TF modes and rename to
	aarch64_mov<mode>high_di
	(aarch64_movtilow_di): Handle TF modes and rename to
	aarch64_mov<mode>low_di
	(aarch64_movtilow_tilow): Remove spurious whitespace.
	* config/aarch64/aarch64.c (aarch64_split_128bit_move): Handle TFmode
	splits.
	(aarch64_print_operand): Update.

From-SVN: r198735
parent 227eb343
2013-05-09 Sofiane Naci <sofiane.naci@arm.com>
* config/aarch64/aarch64.md: New movtf split.
(*movtf_aarch64): Update.
(aarch64_movdi_tilow): Handle TF modes and rename to
aarch64_movdi_<mode>low.
(aarch64_movdi_tihigh): Handle TF modes and rename to
aarch64_movdi_<mode>high
(aarch64_movtihigh_di): Handle TF modes and rename to
aarch64_mov<mode>high_di
(aarch64_movtilow_di): Handle TF modes and rename to
aarch64_mov<mode>low_di
(aarch64_movtilow_tilow): Remove spurious whitespace.
* config/aarch64/aarch64.c (aarch64_split_128bit_move): Handle TFmode
splits.
(aarch64_print_operand): Update.
2013-05-09 Alan Modra <amodra@gmail.com> 2013-05-09 Alan Modra <amodra@gmail.com>
* configure.ac (HAVE_AS_TLS): Enable tests for powerpcle and * configure.ac (HAVE_AS_TLS): Enable tests for powerpcle and
......
...@@ -604,49 +604,85 @@ aarch64_split_128bit_move (rtx dst, rtx src) ...@@ -604,49 +604,85 @@ aarch64_split_128bit_move (rtx dst, rtx src)
{ {
rtx low_dst; rtx low_dst;
gcc_assert (GET_MODE (dst) == TImode); enum machine_mode src_mode = GET_MODE (src);
enum machine_mode dst_mode = GET_MODE (dst);
int src_regno = REGNO (src);
int dst_regno = REGNO (dst);
gcc_assert (dst_mode == TImode || dst_mode == TFmode);
if (REG_P (dst) && REG_P (src)) if (REG_P (dst) && REG_P (src))
{ {
int src_regno = REGNO (src); gcc_assert (src_mode == TImode || src_mode == TFmode);
int dst_regno = REGNO (dst);
gcc_assert (GET_MODE (src) == TImode);
/* Handle r -> w, w -> r. */ /* Handle r -> w, w -> r. */
if (FP_REGNUM_P (dst_regno) && GP_REGNUM_P (src_regno)) if (FP_REGNUM_P (dst_regno) && GP_REGNUM_P (src_regno))
{ {
emit_insn (gen_aarch64_movtilow_di (dst, switch (src_mode) {
gen_lowpart (word_mode, src))); case TImode:
emit_insn (gen_aarch64_movtihigh_di (dst, emit_insn
gen_highpart (word_mode, src))); (gen_aarch64_movtilow_di (dst, gen_lowpart (word_mode, src)));
return; emit_insn
(gen_aarch64_movtihigh_di (dst, gen_highpart (word_mode, src)));
return;
case TFmode:
emit_insn
(gen_aarch64_movtflow_di (dst, gen_lowpart (word_mode, src)));
emit_insn
(gen_aarch64_movtfhigh_di (dst, gen_highpart (word_mode, src)));
return;
default:
gcc_unreachable ();
}
} }
else if (GP_REGNUM_P (dst_regno) && FP_REGNUM_P (src_regno)) else if (GP_REGNUM_P (dst_regno) && FP_REGNUM_P (src_regno))
{ {
emit_insn (gen_aarch64_movdi_tilow (gen_lowpart (word_mode, dst), switch (src_mode) {
src)); case TImode:
emit_insn (gen_aarch64_movdi_tihigh (gen_highpart (word_mode, dst), emit_insn
src)); (gen_aarch64_movdi_tilow (gen_lowpart (word_mode, dst), src));
return; emit_insn
(gen_aarch64_movdi_tihigh (gen_highpart (word_mode, dst), src));
return;
case TFmode:
emit_insn
(gen_aarch64_movdi_tflow (gen_lowpart (word_mode, dst), src));
emit_insn
(gen_aarch64_movdi_tfhigh (gen_highpart (word_mode, dst), src));
return;
default:
gcc_unreachable ();
}
} }
/* Fall through to r -> r cases. */ /* Fall through to r -> r cases. */
} }
low_dst = gen_lowpart (word_mode, dst); switch (dst_mode) {
if (REG_P (low_dst) case TImode:
&& reg_overlap_mentioned_p (low_dst, src)) low_dst = gen_lowpart (word_mode, dst);
{ if (REG_P (low_dst)
aarch64_emit_move (gen_highpart (word_mode, dst), && reg_overlap_mentioned_p (low_dst, src))
gen_highpart_mode (word_mode, TImode, src)); {
aarch64_emit_move (low_dst, gen_lowpart (word_mode, src)); aarch64_emit_move (gen_highpart (word_mode, dst),
} gen_highpart_mode (word_mode, TImode, src));
else aarch64_emit_move (low_dst, gen_lowpart (word_mode, src));
{ }
aarch64_emit_move (low_dst, gen_lowpart (word_mode, src)); else
aarch64_emit_move (gen_highpart (word_mode, dst), {
gen_highpart_mode (word_mode, TImode, src)); aarch64_emit_move (low_dst, gen_lowpart (word_mode, src));
} aarch64_emit_move (gen_highpart (word_mode, dst),
gen_highpart_mode (word_mode, TImode, src));
}
return;
case TFmode:
emit_move_insn (gen_rtx_REG (DFmode, dst_regno),
gen_rtx_REG (DFmode, src_regno));
emit_move_insn (gen_rtx_REG (DFmode, dst_regno + 1),
gen_rtx_REG (DFmode, src_regno + 1));
return;
default:
gcc_unreachable ();
}
} }
bool bool
...@@ -3324,26 +3360,6 @@ aarch64_print_operand (FILE *f, rtx x, char code) ...@@ -3324,26 +3360,6 @@ aarch64_print_operand (FILE *f, rtx x, char code)
asm_fprintf (f, "%s", reg_names [REGNO (x) + 1]); asm_fprintf (f, "%s", reg_names [REGNO (x) + 1]);
break; break;
case 'Q':
/* Print the least significant register of a pair (TImode) of regs. */
if (GET_CODE (x) != REG || !GP_REGNUM_P (REGNO (x) + 1))
{
output_operand_lossage ("invalid operand for '%%%c'", code);
return;
}
asm_fprintf (f, "%s", reg_names [REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)]);
break;
case 'R':
/* Print the most significant register of a pair (TImode) of regs. */
if (GET_CODE (x) != REG || !GP_REGNUM_P (REGNO (x) + 1))
{
output_operand_lossage ("invalid operand for '%%%c'", code);
return;
}
asm_fprintf (f, "%s", reg_names [REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)]);
break;
case 'm': case 'm':
/* Print a condition (eq, ne, etc). */ /* Print a condition (eq, ne, etc). */
......
...@@ -997,9 +997,9 @@ ...@@ -997,9 +997,9 @@
|| register_operand (operands[1], TFmode))" || register_operand (operands[1], TFmode))"
"@ "@
orr\\t%0.16b, %1.16b, %1.16b orr\\t%0.16b, %1.16b, %1.16b
mov\\t%0, %1\;mov\\t%H0, %H1 #
fmov\\t%d0, %Q1\;fmov\\t%0.d[1], %R1 #
fmov\\t%Q0, %d1\;fmov\\t%R0, %1.d[1] #
movi\\t%0.2d, #0 movi\\t%0.2d, #0
fmov\\t%s0, wzr fmov\\t%s0, wzr
ldr\\t%q0, %1 ldr\\t%q0, %1
...@@ -1013,6 +1013,17 @@ ...@@ -1013,6 +1013,17 @@
(set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*")] (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*")]
) )
(define_split
[(set (match_operand:TF 0 "register_operand" "")
(match_operand:TF 1 "aarch64_reg_or_imm" ""))]
"reload_completed && aarch64_split_128bit_move_p (operands[0], operands[1])"
[(const_int 0)]
{
aarch64_split_128bit_move (operands[0], operands[1]);
DONE;
}
)
;; Operands 1 and 3 are tied together by the final condition; so we allow ;; Operands 1 and 3 are tied together by the final condition; so we allow
;; fairly lax checking on the second memory operation. ;; fairly lax checking on the second memory operation.
(define_insn "load_pair<mode>" (define_insn "load_pair<mode>"
...@@ -3550,9 +3561,9 @@ ...@@ -3550,9 +3561,9 @@
;; after or during reload as we don't want these patterns to start ;; after or during reload as we don't want these patterns to start
;; kicking in during the combiner. ;; kicking in during the combiner.
(define_insn "aarch64_movdi_tilow" (define_insn "aarch64_movdi_<mode>low"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(truncate:DI (match_operand:TI 1 "register_operand" "w")))] (truncate:DI (match_operand:TX 1 "register_operand" "w")))]
"reload_completed || reload_in_progress" "reload_completed || reload_in_progress"
"fmov\\t%x0, %d1" "fmov\\t%x0, %d1"
[(set_attr "v8type" "fmovf2i") [(set_attr "v8type" "fmovf2i")
...@@ -3560,10 +3571,10 @@ ...@@ -3560,10 +3571,10 @@
(set_attr "length" "4") (set_attr "length" "4")
]) ])
(define_insn "aarch64_movdi_tihigh" (define_insn "aarch64_movdi_<mode>high"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(truncate:DI (truncate:DI
(lshiftrt:TI (match_operand:TI 1 "register_operand" "w") (lshiftrt:TX (match_operand:TX 1 "register_operand" "w")
(const_int 64))))] (const_int 64))))]
"reload_completed || reload_in_progress" "reload_completed || reload_in_progress"
"fmov\\t%x0, %1.d[1]" "fmov\\t%x0, %1.d[1]"
...@@ -3572,24 +3583,22 @@ ...@@ -3572,24 +3583,22 @@
(set_attr "length" "4") (set_attr "length" "4")
]) ])
(define_insn "aarch64_movtihigh_di" (define_insn "aarch64_mov<mode>high_di"
[(set (zero_extract:TI (match_operand:TI 0 "register_operand" "+w") [(set (zero_extract:TX (match_operand:TX 0 "register_operand" "+w")
(const_int 64) (const_int 64)) (const_int 64) (const_int 64))
(zero_extend:TI (match_operand:DI 1 "register_operand" "r")))] (zero_extend:TX (match_operand:DI 1 "register_operand" "r")))]
"reload_completed || reload_in_progress" "reload_completed || reload_in_progress"
"fmov\\t%0.d[1], %x1" "fmov\\t%0.d[1], %x1"
[(set_attr "v8type" "fmovi2f") [(set_attr "v8type" "fmovi2f")
(set_attr "mode" "DI") (set_attr "mode" "DI")
(set_attr "length" "4") (set_attr "length" "4")
]) ])
(define_insn "aarch64_movtilow_di" (define_insn "aarch64_mov<mode>low_di"
[(set (match_operand:TI 0 "register_operand" "=w") [(set (match_operand:TX 0 "register_operand" "=w")
(zero_extend:TI (match_operand:DI 1 "register_operand" "r")))] (zero_extend:TX (match_operand:DI 1 "register_operand" "r")))]
"reload_completed || reload_in_progress" "reload_completed || reload_in_progress"
"fmov\\t%d0, %x1" "fmov\\t%d0, %x1"
[(set_attr "v8type" "fmovi2f") [(set_attr "v8type" "fmovi2f")
(set_attr "mode" "DI") (set_attr "mode" "DI")
(set_attr "length" "4") (set_attr "length" "4")
...@@ -3601,7 +3610,6 @@ ...@@ -3601,7 +3610,6 @@
(truncate:DI (match_operand:TI 1 "register_operand" "w"))))] (truncate:DI (match_operand:TI 1 "register_operand" "w"))))]
"reload_completed || reload_in_progress" "reload_completed || reload_in_progress"
"fmov\\t%d0, %d1" "fmov\\t%d0, %d1"
[(set_attr "v8type" "fmovi2f") [(set_attr "v8type" "fmovi2f")
(set_attr "mode" "DI") (set_attr "mode" "DI")
(set_attr "length" "4") (set_attr "length" "4")
......
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