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lvzhengyang
riscv-gcc-1
Commits
12249385
Commit
12249385
authored
Mar 14, 2002
by
Richard Earnshaw
Committed by
Richard Earnshaw
Mar 14, 2002
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* arm.md: Fix warnings about constraints in peepholes and splits.
From-SVN: r50786
parent
933a0721
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gcc/ChangeLog
View file @
12249385
2002-03-14 Richard Earnshaw <rearnsha@arm.com>
* arm.md: Fix warnings about constraints in peepholes and splits.
2002-03-14 Zack Weinberg <zack@codesourcery.com>
2002-03-14 Zack Weinberg <zack@codesourcery.com>
* cpphash.h (struct lexer_state): Remove line_extension member.
* cpphash.h (struct lexer_state): Remove line_extension member.
...
...
gcc/config/arm/arm.md
View file @
12249385
...
@@ -596,10 +596,10 @@
...
@@ -596,10 +596,10 @@
;; Reloading and elimination of the frame pointer can
;; Reloading and elimination of the frame pointer can
;; sometimes cause this optimization to be missed.
;; sometimes cause this optimization to be missed.
(define_peephole2
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "
=l
")
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "const_int_operand" "
M
"))
(match_operand:SI 1 "const_int_operand" ""))
(set (match_dup 0)
(set (match_dup 0)
(plus:SI (match_dup 0) (match_operand:SI 2 "register_operand" "
k
")))]
(plus:SI (match_dup 0) (match_operand:SI 2 "register_operand" "")))]
"TARGET_THUMB
"TARGET_THUMB
&& REGNO (operands[2]) == STACK_POINTER_REGNUM
&& REGNO (operands[2]) == STACK_POINTER_REGNUM
&& (unsigned HOST_WIDE_INT) (INTVAL (operands[1])) < 1024
&& (unsigned HOST_WIDE_INT) (INTVAL (operands[1])) < 1024
...
@@ -2334,11 +2334,11 @@
...
@@ -2334,11 +2334,11 @@
; insns.
; insns.
(define_split
(define_split
[
(set (match_operand:SI 0 "s_register_operand" "
=r
")
[
(set (match_operand:SI 0 "s_register_operand" "")
(ior:SI (and:SI (not:SI (match_operand:SI 1 "s_register_operand" "
r
"))
(ior:SI (and:SI (not:SI (match_operand:SI 1 "s_register_operand" ""))
(not:SI (match_operand:SI 2 "arm_rhs_operand" "
rI
")))
(not:SI (match_operand:SI 2 "arm_rhs_operand" "")))
(match_operand:SI 3 "arm_rhs_operand" "
rI
")))
(match_operand:SI 3 "arm_rhs_operand" "")))
(clobber (match_operand:SI 4 "s_register_operand" "
=r
"))]
(clobber (match_operand:SI 4 "s_register_operand" ""))]
"TARGET_ARM"
"TARGET_ARM"
[
(set (match_dup 4) (and:SI (ior:SI (match_dup 1) (match_dup 2))
[
(set (match_dup 4) (and:SI (ior:SI (match_dup 1) (match_dup 2))
(not:SI (match_dup 3))))
(not:SI (match_dup 3))))
...
...
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