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riscv-gcc-1
Commit 11d8d07e by Segher Boessenkool Committed by Segher Boessenkool
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rs6000: Remove TARGET_FPRS 

Since rs6000 no longer supports SPE, TARGET_FPRS now always is true.

This makes TARGET_{SF,DF}_SPE always false.  Many patterns in spe.md
can now be deleted; which makes it possible to merge e.g. negdd2 with
*negdd2_fpr.

Finally, e500.h is deleted (it isn't used).


	* config/rs6000/darwin.md: Replace TARGET_FPRS by 1 and simplify.
	* config/rs6000/dfp.md: Ditto.
	(negdd2, *negdd2_fpr): Merge.
	(absdd2, *absdd2_fpr): Merge.
	(negtd2, *negtd2_fpr): Merge.
	(abstd2, *abstd2_fpr): Merge.
	* config/rs6000/e500.h: Delete file.
	* config/rs6000/predicates.md (rs6000_cbranch_operator): Replace
	TARGET_FPRS by 1 and simplify.
	* config/rs6000/rs6000-c.c: Ditto.
	* config/rs6000/rs6000.c: Ditto.  Also replace TARGET_SF_SPE and
	TARGET_DF_SPE by 0.
	* config/rs6000/rs6000.h: Ditto.  Delete TARGET_SF_SPE and
	TARGET_DF_SPE.
	* config/rs6000/rs6000.md: Ditto.
	(floatdidf2, *floatdidf2_fpr): Merge.
	(move_from_CR_gt_bit): Delete.
	* config/rs6000/spe.md: Replace TARGET_FPRS by 1 and simplify.
	(E500_CR_IOR_COMPARE): Delete.
	(All patterns that require !TARGET_FPRS): Delete.
	* config/rs6000/vsx.md: Replace TARGET_FPRS by 1 and simplify.

From-SVN: r248974
parent a6d31e84
Showing with 64 additions and 258 deletions
gcc/ChangeLog
2017-06-07 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/darwin.md: Replace TARGET_FPRS by 1 and simplify.
* config/rs6000/dfp.md: Ditto.
(negdd2, *negdd2_fpr): Merge.
(absdd2, *absdd2_fpr): Merge.
(negtd2, *negtd2_fpr): Merge.
(abstd2, *abstd2_fpr): Merge.
* config/rs6000/e500.h: Delete file.
* config/rs6000/predicates.md (rs6000_cbranch_operator): Replace
TARGET_FPRS by 1 and simplify.
* config/rs6000/rs6000-c.c: Ditto.
* config/rs6000/rs6000.c: Ditto. Also replace TARGET_SF_SPE and
TARGET_DF_SPE by 0.
* config/rs6000/rs6000.h: Ditto. Delete TARGET_SF_SPE and
TARGET_DF_SPE.
* config/rs6000/rs6000.md: Ditto.
(floatdidf2, *floatdidf2_fpr): Merge.
(move_from_CR_gt_bit): Delete.
* config/rs6000/spe.md: Replace TARGET_FPRS by 1 and simplify.
(E500_CR_IOR_COMPARE): Delete.
(All patterns that require !TARGET_FPRS): Delete.
* config/rs6000/vsx.md: Replace TARGET_FPRS by 1 and simplify.
2017-06-07 Bin Cheng <bin.cheng@arm.com> 2017-06-07 Bin Cheng <bin.cheng@arm.com>
* passes.def (pass_iv_canon): Move before pass_loop_distribution. * passes.def (pass_iv_canon): Move before pass_loop_distribution.
......
gcc/config/rs6000/darwin.md
...@@ -30,7 +30,7 @@ You should have received a copy of the GNU General Public License ...@@ -30,7 +30,7 @@ You should have received a copy of the GNU General Public License
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
(mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))] (match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_64BIT" "TARGET_MACHO && TARGET_HARD_FLOAT && !TARGET_64BIT"
"* "*
{ {
switch (which_alternative) switch (which_alternative)
...@@ -61,7 +61,7 @@ You should have received a copy of the GNU General Public License ...@@ -61,7 +61,7 @@ You should have received a copy of the GNU General Public License
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
(mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))] (match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT" "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
"* "*
{ {
switch (which_alternative) switch (which_alternative)
...@@ -81,7 +81,7 @@ You should have received a copy of the GNU General Public License ...@@ -81,7 +81,7 @@ You should have received a copy of the GNU General Public License
[(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" ""))) (match_operand 2 "" "")))
(match_operand:DF 0 "gpc_reg_operand" "f"))] (match_operand:DF 0 "gpc_reg_operand" "f"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
"stfd %0,lo16(%2)(%1)" "stfd %0,lo16(%2)(%1)"
[(set_attr "type" "store") [(set_attr "type" "store")
(set_attr "length" "4")]) (set_attr "length" "4")])
...@@ -90,7 +90,7 @@ You should have received a copy of the GNU General Public License ...@@ -90,7 +90,7 @@ You should have received a copy of the GNU General Public License
[(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b") [(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
(match_operand 2 "" ""))) (match_operand 2 "" "")))
(match_operand:DF 0 "gpc_reg_operand" "f"))] (match_operand:DF 0 "gpc_reg_operand" "f"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT" "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
"stfd %0,lo16(%2)(%1)" "stfd %0,lo16(%2)(%1)"
[(set_attr "type" "store") [(set_attr "type" "store")
(set_attr "length" "4")]) (set_attr "length" "4")])
...@@ -99,7 +99,7 @@ You should have received a copy of the GNU General Public License ...@@ -99,7 +99,7 @@ You should have received a copy of the GNU General Public License
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
(mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))] (match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
"@ "@
lfs %0,lo16(%2)(%1) lfs %0,lo16(%2)(%1)
lwz %0,lo16(%2)(%1)" lwz %0,lo16(%2)(%1)"
...@@ -110,7 +110,7 @@ You should have received a copy of the GNU General Public License ...@@ -110,7 +110,7 @@ You should have received a copy of the GNU General Public License
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
(mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))] (match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT" "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
"@ "@
lfs %0,lo16(%2)(%1) lfs %0,lo16(%2)(%1)
lwz %0,lo16(%2)(%1)" lwz %0,lo16(%2)(%1)"
...@@ -121,7 +121,7 @@ You should have received a copy of the GNU General Public License ...@@ -121,7 +121,7 @@ You should have received a copy of the GNU General Public License
[(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))) (match_operand 2 "" "")))
(match_operand:SF 0 "gpc_reg_operand" "f,!r"))] (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
"@ "@
stfs %0,lo16(%2)(%1) stfs %0,lo16(%2)(%1)
stw %0,lo16(%2)(%1)" stw %0,lo16(%2)(%1)"
...@@ -132,7 +132,7 @@ You should have received a copy of the GNU General Public License ...@@ -132,7 +132,7 @@ You should have received a copy of the GNU General Public License
[(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") [(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))) (match_operand 2 "" "")))
(match_operand:SF 0 "gpc_reg_operand" "f,!r"))] (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT" "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
"@ "@
stfs %0,lo16(%2)(%1) stfs %0,lo16(%2)(%1)
stw %0,lo16(%2)(%1)" stw %0,lo16(%2)(%1)"
......
gcc/config/rs6000/dfp.md
...@@ -35,7 +35,7 @@ ...@@ -35,7 +35,7 @@
UNSPEC_MOVSD_STORE))] UNSPEC_MOVSD_STORE))]
"(gpc_reg_operand (operands[0], DDmode) "(gpc_reg_operand (operands[0], DDmode)
|| gpc_reg_operand (operands[1], SDmode)) || gpc_reg_operand (operands[1], SDmode))
&& TARGET_HARD_FLOAT && TARGET_FPRS" && TARGET_HARD_FLOAT"
"stfd%U0%X0 %1,%0" "stfd%U0%X0 %1,%0"
[(set_attr "type" "fpstore") [(set_attr "type" "fpstore")
(set_attr "length" "4")]) (set_attr "length" "4")])
...@@ -46,7 +46,7 @@ ...@@ -46,7 +46,7 @@
UNSPEC_MOVSD_LOAD))] UNSPEC_MOVSD_LOAD))]
"(gpc_reg_operand (operands[0], SDmode) "(gpc_reg_operand (operands[0], SDmode)
|| gpc_reg_operand (operands[1], DDmode)) || gpc_reg_operand (operands[1], DDmode))
&& TARGET_HARD_FLOAT && TARGET_FPRS" && TARGET_HARD_FLOAT"
"lfd%U1%X1 %0,%1" "lfd%U1%X1 %0,%1"
[(set_attr "type" "fpload") [(set_attr "type" "fpload")
(set_attr "length" "4")]) (set_attr "length" "4")])
...@@ -78,65 +78,41 @@ ...@@ -78,65 +78,41 @@
"drsp %0,%1" "drsp %0,%1"
[(set_attr "type" "dfp")]) [(set_attr "type" "dfp")])
(define_expand "negdd2" (define_insn "negdd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "")
(neg:DD (match_operand:DD 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"")
(define_insn "*negdd2_fpr"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d") [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))] (neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT"
"fneg %0,%1" "fneg %0,%1"
[(set_attr "type" "fpsimple")]) [(set_attr "type" "fpsimple")])
(define_expand "absdd2" (define_insn "absdd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "")
(abs:DD (match_operand:DD 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"")
(define_insn "*absdd2_fpr"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d") [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))] (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT"
"fabs %0,%1" "fabs %0,%1"
[(set_attr "type" "fpsimple")]) [(set_attr "type" "fpsimple")])
(define_insn "*nabsdd2_fpr" (define_insn "*nabsdd2_fpr"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d") [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))] (neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT"
"fnabs %0,%1" "fnabs %0,%1"
[(set_attr "type" "fpsimple")]) [(set_attr "type" "fpsimple")])
(define_expand "negtd2" (define_insn "negtd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "")
(neg:TD (match_operand:TD 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"")
(define_insn "*negtd2_fpr"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d,d") [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
(neg:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))] (neg:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT"
"@ "@
fneg %0,%1 fneg %0,%1
fneg %0,%1\;fmr %L0,%L1" fneg %0,%1\;fmr %L0,%L1"
[(set_attr "type" "fpsimple") [(set_attr "type" "fpsimple")
(set_attr "length" "4,8")]) (set_attr "length" "4,8")])
(define_expand "abstd2" (define_insn "abstd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "")
(abs:TD (match_operand:TD 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"")
(define_insn "*abstd2_fpr"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d,d") [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
(abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))] (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT"
"@ "@
fabs %0,%1 fabs %0,%1
fabs %0,%1\;fmr %L0,%L1" fabs %0,%1\;fmr %L0,%L1"
...@@ -146,7 +122,7 @@ ...@@ -146,7 +122,7 @@
(define_insn "*nabstd2_fpr" (define_insn "*nabstd2_fpr"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d,d") [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
(neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))] (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT"
"@ "@
fnabs %0,%1 fnabs %0,%1
fnabs %0,%1\;fmr %L0,%L1" fnabs %0,%1\;fmr %L0,%L1"
......
gcc/config/rs6000/predicates.md
...@@ -1240,16 +1240,8 @@ ...@@ -1240,16 +1240,8 @@
1")))) 1"))))
;; Return 1 if OP is a valid comparison operator for "cbranch" instructions. ;; Return 1 if OP is a valid comparison operator for "cbranch" instructions.
;; If we're assuming that FP operations cannot generate user-visible traps,
;; then on e500 we can use the ordered-signaling instructions to implement
;; the unordered-quiet FP comparison predicates modulo a reversal.
(define_predicate "rs6000_cbranch_operator" (define_predicate "rs6000_cbranch_operator"
(if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS") (match_operand 0 "comparison_operator"))
(if_then_else (match_test "flag_trapping_math")
(match_operand 0 "ordered_comparison_operator")
(ior (match_operand 0 "ordered_comparison_operator")
(match_code ("unlt,unle,ungt,unge"))))
(match_operand 0 "comparison_operator")))
;; Return 1 if OP is an unsigned comparison operator. ;; Return 1 if OP is an unsigned comparison operator.
(define_predicate "unsigned_comparison_operator" (define_predicate "unsigned_comparison_operator"
......
gcc/config/rs6000/rs6000-c.c
...@@ -488,10 +488,10 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, ...@@ -488,10 +488,10 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
the following conditions: the following conditions:
1. The operating system does not support saving of AltiVec 1. The operating system does not support saving of AltiVec
registers (OS_MISSING_ALTIVEC). registers (OS_MISSING_ALTIVEC).
2. If any of the options TARGET_HARD_FLOAT, TARGET_FPRS, 2. If any of the options TARGET_HARD_FLOAT, TARGET_SINGLE_FLOAT,
TARGET_SINGLE_FLOAT, or TARGET_DOUBLE_FLOAT are turned off. or TARGET_DOUBLE_FLOAT are turned off. Hereafter, the
Hereafter, the OPTION_MASK_VSX flag is considered to have been OPTION_MASK_VSX flag is considered to have been turned off
turned off explicitly. explicitly.
3. If TARGET_PAIRED_FLOAT was enabled. Hereafter, the 3. If TARGET_PAIRED_FLOAT was enabled. Hereafter, the
OPTION_MASK_VSX flag is considered to have been turned off OPTION_MASK_VSX flag is considered to have been turned off
explicitly. explicitly.
...@@ -674,8 +674,8 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile) ...@@ -674,8 +674,8 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand; cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand;
} }
} }
if ((!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE))) if (!TARGET_HARD_FLOAT
||(TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_DOUBLE_FLOAT)) || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT))
builtin_define ("_SOFT_DOUBLE"); builtin_define ("_SOFT_DOUBLE");
/* Used by lwarx/stwcx. errata work-around. */ /* Used by lwarx/stwcx. errata work-around. */
if (rs6000_cpu == PROCESSOR_PPC405) if (rs6000_cpu == PROCESSOR_PPC405)
...@@ -775,7 +775,7 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile) ...@@ -775,7 +775,7 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__"); builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__");
/* Let the compiled code know if 'f' class registers will not be available. */ /* Let the compiled code know if 'f' class registers will not be available. */
if (TARGET_SOFT_FLOAT || !TARGET_FPRS) if (TARGET_SOFT_FLOAT)
builtin_define ("__NO_FPRS__"); builtin_define ("__NO_FPRS__");
/* Whether aggregates passed by value are aligned to a 16 byte boundary /* Whether aggregates passed by value are aligned to a 16 byte boundary
......
gcc/config/rs6000/rs6000.h
...@@ -449,8 +449,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); ...@@ -449,8 +449,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
#define FLOAT128_IBM_P(MODE) \ #define FLOAT128_IBM_P(MODE) \
((!TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \ ((!TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \
|| (TARGET_HARD_FLOAT && TARGET_FPRS \ || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode)))
&& ((MODE) == IFmode || (MODE) == ICmode)))
/* Helper macros to say whether a 128-bit floating point type can go in a /* Helper macros to say whether a 128-bit floating point type can go in a
single vector register, or whether it needs paired scalar values. */ single vector register, or whether it needs paired scalar values. */
...@@ -573,7 +572,6 @@ extern int rs6000_vector_align[]; ...@@ -573,7 +572,6 @@ extern int rs6000_vector_align[];
#define TARGET_SPE_ABI 0 #define TARGET_SPE_ABI 0
#define TARGET_SPE 0 #define TARGET_SPE 0
#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64) #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
#define TARGET_FPRS 1
#define TARGET_E500_SINGLE 0 #define TARGET_E500_SINGLE 0
#define TARGET_E500_DOUBLE 0 #define TARGET_E500_DOUBLE 0
#define CHECK_E500_OPTIONS do { } while (0) #define CHECK_E500_OPTIONS do { } while (0)
...@@ -724,39 +722,26 @@ extern int rs6000_vector_align[]; ...@@ -724,39 +722,26 @@ extern int rs6000_vector_align[];
|| rs6000_cpu == PROCESSOR_PPC8548) || rs6000_cpu == PROCESSOR_PPC8548)
/* Whether SF/DF operations are supported on the E500. */
#define TARGET_SF_SPE (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT \
&& !TARGET_FPRS)
#define TARGET_DF_SPE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \
&& !TARGET_FPRS && TARGET_E500_DOUBLE)
/* Whether SF/DF operations are supported by the normal floating point unit /* Whether SF/DF operations are supported by the normal floating point unit
(or the vector/scalar unit). */ (or the vector/scalar unit). */
#define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \ #define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT)
&& TARGET_SINGLE_FLOAT) #define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
#define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \
&& TARGET_DOUBLE_FLOAT)
/* Whether SF/DF operations are supported by any hardware. */ /* Whether SF/DF operations are supported by any hardware. */
#define TARGET_SF_INSN (TARGET_SF_FPR || TARGET_SF_SPE) #define TARGET_SF_INSN TARGET_SF_FPR
#define TARGET_DF_INSN (TARGET_DF_FPR || TARGET_DF_SPE) #define TARGET_DF_INSN TARGET_DF_FPR
/* Which machine supports the various reciprocal estimate instructions. */ /* Which machine supports the various reciprocal estimate instructions. */
#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
&& TARGET_FPRS && TARGET_SINGLE_FLOAT) && TARGET_SINGLE_FLOAT)
#define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \ #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \
&& TARGET_DOUBLE_FLOAT \
&& (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
&& TARGET_PPC_GFXOPT && TARGET_FPRS \ && TARGET_PPC_GFXOPT && TARGET_SINGLE_FLOAT)
&& TARGET_SINGLE_FLOAT)
#define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \ #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \
&& TARGET_DOUBLE_FLOAT \
&& (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
/* Conditions to allow TOC fusion for loading/storing integers. */ /* Conditions to allow TOC fusion for loading/storing integers. */
...@@ -771,7 +756,6 @@ extern int rs6000_vector_align[]; ...@@ -771,7 +756,6 @@ extern int rs6000_vector_align[];
&& (TARGET_CMODEL != CMODEL_SMALL) \ && (TARGET_CMODEL != CMODEL_SMALL) \
&& TARGET_POWERPC64 \ && TARGET_POWERPC64 \
&& TARGET_HARD_FLOAT \ && TARGET_HARD_FLOAT \
&& TARGET_FPRS \
&& TARGET_SINGLE_FLOAT \ && TARGET_SINGLE_FLOAT \
&& TARGET_DOUBLE_FLOAT) && TARGET_DOUBLE_FLOAT)
...@@ -1875,7 +1859,7 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; ...@@ -1875,7 +1859,7 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
#define FUNCTION_VALUE_REGNO_P(N) \ #define FUNCTION_VALUE_REGNO_P(N) \
((N) == GP_ARG_RETURN \ ((N) == GP_ARG_RETURN \
|| (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \ || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \
&& TARGET_HARD_FLOAT && TARGET_FPRS) \ && TARGET_HARD_FLOAT) \
|| (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \ || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \
&& TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
...@@ -1887,7 +1871,7 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; ...@@ -1887,7 +1871,7 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
|| (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \ || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \
&& TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
|| (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \ || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \
&& TARGET_HARD_FLOAT && TARGET_FPRS)) && TARGET_HARD_FLOAT))
/* Define a data type for recording info about an argument list /* Define a data type for recording info about an argument list
during the scan of that argument list. This data type should during the scan of that argument list. This data type should
......
gcc/config/rs6000/spe.md
...@@ -31,7 +31,6 @@ ...@@ -31,7 +31,6 @@
(TSTTFGT_GPR 1015) (TSTTFGT_GPR 1015)
(CMPTFLT_GPR 1016) (CMPTFLT_GPR 1016)
(TSTTFLT_GPR 1017) (TSTTFLT_GPR 1017)
(E500_CR_IOR_COMPARE 1018)
]) ])
;; Modes using a 64-bit register. ;; Modes using a 64-bit register.
...@@ -43,59 +42,6 @@ ...@@ -43,59 +42,6 @@
;; DImode and TImode. ;; DImode and TImode.
(define_mode_iterator DITI [DI TI]) (define_mode_iterator DITI [DI TI])
(define_insn "*negsf2_gpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsneg %0,%1"
[(set_attr "type" "fpsimple")])
(define_insn "*abssf2_gpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsabs %0,%1"
[(set_attr "type" "fpsimple")])
(define_insn "*nabssf2_gpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsnabs %0,%1"
[(set_attr "type" "fpsimple")])
(define_insn "*addsf3_gpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
(match_operand:SF 2 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsadd %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "*subsf3_gpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(minus:SF (match_operand:SF 1 "gpc_reg_operand" "r")
(match_operand:SF 2 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efssub %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "*mulsf3_gpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
(match_operand:SF 2 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsmul %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "*divsf3_gpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(div:SF (match_operand:SF 1 "gpc_reg_operand" "r")
(match_operand:SF 2 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsdiv %0,%1,%2"
[(set_attr "type" "vecfdiv")])
;; Floating point conversion instructions. ;; Floating point conversion instructions.
(define_insn "spe_fixuns_truncdfsi2" (define_insn "spe_fixuns_truncdfsi2"
...@@ -112,20 +58,6 @@ ...@@ -112,20 +58,6 @@
"efdcfs %0,%1" "efdcfs %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "spe_fixuns_truncsfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsctuiz %0,%1"
[(set_attr "type" "fp")])
(define_insn "spe_fix_truncsfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsctsiz %0,%1"
[(set_attr "type" "fp")])
(define_insn "spe_fix_truncdfsi2" (define_insn "spe_fix_truncdfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))] (fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
...@@ -133,13 +65,6 @@ ...@@ -133,13 +65,6 @@
"efdctsiz %0,%1" "efdctsiz %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "spe_floatunssisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efscfui %0,%1"
[(set_attr "type" "fp")])
(define_insn "spe_floatunssidf2" (define_insn "spe_floatunssidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=r") [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
...@@ -147,13 +72,6 @@ ...@@ -147,13 +72,6 @@
"efdcfui %0,%1" "efdcfui %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "spe_floatsisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efscfsi %0,%1"
[(set_attr "type" "fp")])
(define_insn "spe_floatsidf2" (define_insn "spe_floatsidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=r") [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
...@@ -3233,88 +3151,10 @@ ...@@ -3233,88 +3151,10 @@
"mfspefscr %0" "mfspefscr %0"
[(set_attr "type" "vecsimple")]) [(set_attr "type" "vecsimple")])
;; Flip the GT bit.
(define_insn "e500_flip_gt_bit"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(unspec:CCFP
[(match_operand:CCFP 1 "cc_reg_operand" "y")] 999))]
"!TARGET_FPRS && TARGET_HARD_FLOAT"
"*
{
return output_e500_flip_gt_bit (operands[0], operands[1]);
}"
[(set_attr "type" "cr_logical")])
;; MPC8540 single-precision FP instructions on GPRs. ;; MPC8540 single-precision FP instructions on GPRs.
;; We have 2 variants for each. One for IEEE compliant math and one ;; We have 2 variants for each. One for IEEE compliant math and one
;; for non IEEE compliant math. ;; for non IEEE compliant math.
(define_insn "cmpsfeq_gpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(unspec:CCFP
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
(match_operand:SF 2 "gpc_reg_operand" "r"))]
1000))]
"TARGET_HARD_FLOAT && !TARGET_FPRS
&& !(flag_finite_math_only && !flag_trapping_math)"
"efscmpeq %0,%1,%2"
[(set_attr "type" "veccmp")])
(define_insn "tstsfeq_gpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(unspec:CCFP
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
(match_operand:SF 2 "gpc_reg_operand" "r"))]
1001))]
"TARGET_HARD_FLOAT && !TARGET_FPRS
&& flag_finite_math_only && !flag_trapping_math"
"efststeq %0,%1,%2"
[(set_attr "type" "veccmpsimple")])
(define_insn "cmpsfgt_gpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(unspec:CCFP
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
(match_operand:SF 2 "gpc_reg_operand" "r"))]
1002))]
"TARGET_HARD_FLOAT && !TARGET_FPRS
&& !(flag_finite_math_only && !flag_trapping_math)"
"efscmpgt %0,%1,%2"
[(set_attr "type" "veccmp")])
(define_insn "tstsfgt_gpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(unspec:CCFP
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
(match_operand:SF 2 "gpc_reg_operand" "r"))]
1003))]
"TARGET_HARD_FLOAT && !TARGET_FPRS
&& flag_finite_math_only && !flag_trapping_math"
"efststgt %0,%1,%2"
[(set_attr "type" "veccmpsimple")])
(define_insn "cmpsflt_gpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(unspec:CCFP
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
(match_operand:SF 2 "gpc_reg_operand" "r"))]
1004))]
"TARGET_HARD_FLOAT && !TARGET_FPRS
&& !(flag_finite_math_only && !flag_trapping_math)"
"efscmplt %0,%1,%2"
[(set_attr "type" "veccmp")])
(define_insn "tstsflt_gpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(unspec:CCFP
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
(match_operand:SF 2 "gpc_reg_operand" "r"))]
1005))]
"TARGET_HARD_FLOAT && !TARGET_FPRS
&& flag_finite_math_only && !flag_trapping_math"
"efststlt %0,%1,%2"
[(set_attr "type" "veccmpsimple")])
;; Same thing, but for double-precision. ;; Same thing, but for double-precision.
(define_insn "cmpdfeq_gpr" (define_insn "cmpdfeq_gpr"
...@@ -3463,16 +3303,6 @@ ...@@ -3463,16 +3303,6 @@
[(set_attr "type" "veccmpsimple") [(set_attr "type" "veccmpsimple")
(set_attr "length" "20")]) (set_attr "length" "20")])
;; Like cceq_ior_compare, but compare the GT bits.
(define_insn "e500_cr_ior_compare"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(unspec:CCFP [(match_operand 1 "cc_reg_operand" "y")
(match_operand 2 "cc_reg_operand" "y")]
E500_CR_IOR_COMPARE))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"cror 4*%0+gt,4*%1+gt,4*%2+gt"
[(set_attr "type" "cr_logical")])
;; Out-of-line prologues and epilogues. ;; Out-of-line prologues and epilogues.
(define_insn "*save_gpregs_spe" (define_insn "*save_gpregs_spe"
[(match_parallel 0 "any_parallel_operand" [(match_parallel 0 "any_parallel_operand"
......
gcc/config/rs6000/vsx.md
...@@ -1984,7 +1984,7 @@ ...@@ -1984,7 +1984,7 @@
(float:V2DF (float:V2DF
(fix:V2DI (fix:V2DI
(match_operand:V2DF 1 "vsx_register_operand" "wd,?wa"))))] (match_operand:V2DF 1 "vsx_register_operand" "wd,?wa"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& VECTOR_UNIT_VSX_P (V2DFmode) && flag_unsafe_math_optimizations && VECTOR_UNIT_VSX_P (V2DFmode) && flag_unsafe_math_optimizations
&& !flag_trapping_math && TARGET_FRIZ" && !flag_trapping_math && TARGET_FRIZ"
"xvrdpiz %x0,%x1" "xvrdpiz %x0,%x1"
......
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