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lvzhengyang
riscv-gcc-1
Commits
11a802bf
Commit
11a802bf
authored
Oct 26, 2001
by
Kazu Hirata
Committed by
Kazu Hirata
Oct 26, 2001
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* config/h8300/h8300.md (4 anonymous patterns): New.
From-SVN: r46554
parent
cb33eb17
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gcc/ChangeLog
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gcc/config/h8300/h8300.md
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gcc/ChangeLog
View file @
11a802bf
2001
-
10
-
26
Kazu
Hirata
<
kazu
@hxi
.
com
>
2001
-
10
-
26
Kazu
Hirata
<
kazu
@hxi
.
com
>
*
config
/
h8300
/
h8300
.
md
(
4
anonymous
patterns
)
:
New
.
2001
-
10
-
26
Kazu
Hirata
<
kazu
@hxi
.
com
>
*
config
/
h8300
/
h8300
.
c
(
get_shift_alg
)
:
Clean
up
.
Return
the
*
config
/
h8300
/
h8300
.
c
(
get_shift_alg
)
:
Clean
up
.
Return
the
algorithm
through
the
shift_info
structure
.
algorithm
through
the
shift_info
structure
.
(
emit_a_shift
)
:
Update
the
use
of
get_shift_alg
.
(
emit_a_shift
)
:
Update
the
use
of
get_shift_alg
.
...
...
gcc/config/h8300/h8300.md
View file @
11a802bf
...
@@ -2289,3 +2289,69 @@
...
@@ -2289,3 +2289,69 @@
[
(set_attr "cc" "clobber")
[
(set_attr "cc" "clobber")
(set_attr "length" "6")
(set_attr "length" "6")
(set_attr "adjust_length" "no")])
(set_attr "adjust_length" "no")])
;; -----------------------------------------------------------------
;; COMBINE PATTERNS
;; -----------------------------------------------------------------
(define_insn ""
[
(set (match_operand:HI 0 "register_operand" "=r")
(ior:HI
(zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
(match_operand:HI 2 "register_operand" "0")))]
"REGNO (operands
[
0
]
) != REGNO (operands
[
1
]
)"
"or
\\
t%X1,%s0"
[
(set_attr "cc" "clobber")
(set_attr "length" "2")])
(define_insn ""
[
(set (match_operand:SI 0 "register_operand" "=r")
(ior:SI
(zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
(match_operand:SI 2 "register_operand" "0")))]
"(TARGET_H8300H || TARGET_H8300S)
&& (REGNO (operands
[
0
]
) != REGNO (operands
[
1
]
))"
"or.w
\\
t%T1,%f0"
[
(set_attr "cc" "clobber")
(set_attr "length" "2")])
(define_insn ""
[
(set (match_operand:SI 0 "register_operand" "=r")
(ior:SI
(zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
(match_operand:SI 2 "register_operand" "0")))]
"REGNO (operands
[
0
]
) != REGNO (operands
[
1
]
)"
"or
\\
t%X1,%s0"
[
(set_attr "cc" "clobber")
(set_attr "length" "2")])
(define_insn ""
[
(set (match_operand:HI 0 "register_operand" "=r")
(xor:HI
(zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
(match_operand:HI 2 "register_operand" "0")))]
"REGNO (operands
[
0
]
) != REGNO (operands
[
1
]
)"
"xor
\\
t%X1,%s0"
[
(set_attr "cc" "clobber")
(set_attr "length" "2")])
(define_insn ""
[
(set (match_operand:SI 0 "register_operand" "=r")
(xor:SI
(zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
(match_operand:SI 2 "register_operand" "0")))]
"(TARGET_H8300H || TARGET_H8300S)
&& (REGNO (operands
[
0
]
) != REGNO (operands
[
1
]
))"
"xor.w
\\
t%T1,%f0"
[
(set_attr "cc" "clobber")
(set_attr "length" "2")])
(define_insn ""
[
(set (match_operand:SI 0 "register_operand" "=r")
(xor:SI
(zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
(match_operand:SI 2 "register_operand" "0")))]
"REGNO (operands
[
0
]
) != REGNO (operands
[
1
]
)"
"xor
\\
t%X1,%s0"
[
(set_attr "cc" "clobber")
(set_attr "length" "2")])
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