config.gcc: Add support for --with-cpu option for bdver1.

2010-05-14  Harsha Jagasia  <harsha.jagasia@amd.com>

	* config.gcc: Add support for --with-cpu option for bdver1.
	* config/i386/i386.h (TARGET_BDVER1): New macro.
	(ix86_tune_indices): Change SSE_UNALIGNED_MOVE_OPTIMAL
	to SSE_UNALIGNED_LOAD_OPTIMAL. Add SSE_UNALIGNED_STORE_OPTIMAL.
	(ix86_tune_features) :Change SSE_UNALIGNED_MOVE_OPTIMAL
	to SSE_UNALIGNED_LOAD_OPTIMAL. Add SSE_UNALIGNED_STORE_OPTIMAL.
	Add SSE_PACKED_SINGLE_INSN_OPTIMAL.
	(TARGET_CPU_DEFAULT_NAMES): Add bdver1.
	(processor_type): Add PROCESSOR_BDVER1.
	* config/i386/i386.md: Add bdver1 as a new cpu attribute to match
	processor_type in config/i386/i386.h.
	Add check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit
	movaps <reg, reg> instead of movapd <reg, reg> when replacing
	movsd <reg, reg> or movss <reg, reg> for SSE and AVX.
	Add check for  TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
	to emit packed xor instead of packed double/packed integer
	xor for SSE and AVX when moving a zero value.
	* config/i386/sse.md: Add check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
	 to emit movaps instead of movapd/movdqa for SSE and AVX.
	Add check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit packed single
	logical operations i.e and, or and xor instead of packed double logical
	operations for SSE and AVX. 
	* config/i386/i386-c.c: 
	(ix86_target_macros_internal): Add PROCESSOR_BDVER1.
	* config/i386/driver-i386.c: Turn on -mtune=native for BDVER1.
	(has_fma4, has_xop): New.
	* config/i386/i386.c (bdver1_cost): New variable.
	(m_BDVER1): New macro.
	(m_AMD_MULTIPLE): Add m_BDVER1.
	(x86_tune_use_leave, x86_tune_push_memory, x86_tune_unroll_strlen,
	 x86_tune_deep_branch_prediction, x86_tune_use_sahf, x86_tune_movx,
	 x86_tune_use_simode_fiop, x86_tune_promote_qimode, 
	 x86_tune_add_esp_8, x86_tune_tune_sub_esp_4, x86_tune_sub_esp_8,
	 x86_tune_integer_dfmode_moves, x86_tune_partial_reg_dependency,
	 x86_tune_sse_partial_reg_dependency, x86_tune_sse_unaligned_load_optimal,
	 x86_tune_sse_unaligned_store_optimal, x86_tune_sse_typeless_stores,
	 x86_tune_memory_mismatch_stall, x86_tune_use_ffreep,
	 x86_tune_inter_unit_moves, x86_tune_inter_unit_conversions,
	 x86_tune_use_bt, x86_tune_pad_returns, x86_tune_slow_imul_imm32_mem,
	 x86_tune_slow_imul_imm8, x86_tune_fuse_cmp_and_branch): 
	Enable/disable for bdver1.
	(processor_target_table): Add bdver1_cost.
	(cpu_names): Add bdver1.
	(override_options): Set up PROCESSOR_BDVER1 for bdver1 entry in
	 processor_alias_table.
	(ix86_expand_vector_move_misalign): Change 
	 TARGET_SSE_UNALIGNED_MOVE_OPTIMAL to TARGET_SSE_UNALIGNED_LOAD_OPTIMAL.
	 Check for TARGET_SSE_UNALIGNED_STORE_OPTIMAL.
	 Check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit movups instead
	 of movupd/movdqu for SSE and AVX.
	(ix86_tune_issue_rate): Add PROCESSOR_BDVER1.
	(ix86_tune_adjust_cost): Add code for bdver1.
	(standard_sse_constant_opcode): Add check for
	TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit packed single xor instead
	of packed double xor for SSE and AVX.

From-SVN: r159399

gcc/ChangeLog

+2010-05-14  Harsha Jagasia  <harsha.jagasia@amd.com>
+
+	* config.gcc: Add support for --with-cpu option for bdver1.
+	* config/i386/i386.h (TARGET_BDVER1): New macro.
+	(ix86_tune_indices): Change SSE_UNALIGNED_MOVE_OPTIMAL
+	to SSE_UNALIGNED_LOAD_OPTIMAL. Add SSE_UNALIGNED_STORE_OPTIMAL.
+	(ix86_tune_features) :Change SSE_UNALIGNED_MOVE_OPTIMAL
+	to SSE_UNALIGNED_LOAD_OPTIMAL. Add SSE_UNALIGNED_STORE_OPTIMAL.
+	Add SSE_PACKED_SINGLE_INSN_OPTIMAL.
+	(TARGET_CPU_DEFAULT_NAMES): Add bdver1.
+	(processor_type): Add PROCESSOR_BDVER1.
+	* config/i386/i386.md: Add bdver1 as a new cpu attribute to match
+	processor_type in config/i386/i386.h.
+	Add check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit
+	movaps <reg, reg> instead of movapd <reg, reg> when replacing
+	movsd <reg, reg> or movss <reg, reg> for SSE and AVX.
+	Add check for  TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
+	to emit packed xor instead of packed double/packed integer
+	xor for SSE and AVX when moving a zero value.
+	* config/i386/sse.md: Add check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
+	 to emit movaps instead of movapd/movdqa for SSE and AVX.
+	Add check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit packed single
+	logical operations i.e and, or and xor instead of packed double logical
+	operations for SSE and AVX. 
+	* config/i386/i386-c.c: 
+	(ix86_target_macros_internal): Add PROCESSOR_BDVER1.
+	* config/i386/driver-i386.c: Turn on -mtune=native for BDVER1.
+	(has_fma4, has_xop): New.
+	* config/i386/i386.c (bdver1_cost): New variable.
+	(m_BDVER1): New macro.
+	(m_AMD_MULTIPLE): Add m_BDVER1.
+	(x86_tune_use_leave, x86_tune_push_memory, x86_tune_unroll_strlen,
+	 x86_tune_deep_branch_prediction, x86_tune_use_sahf, x86_tune_movx,
+	 x86_tune_use_simode_fiop, x86_tune_promote_qimode, 
+	 x86_tune_add_esp_8, x86_tune_tune_sub_esp_4, x86_tune_sub_esp_8,
+	 x86_tune_integer_dfmode_moves, x86_tune_partial_reg_dependency,
+	 x86_tune_sse_partial_reg_dependency, x86_tune_sse_unaligned_load_optimal,
+	 x86_tune_sse_unaligned_store_optimal, x86_tune_sse_typeless_stores,
+	 x86_tune_memory_mismatch_stall, x86_tune_use_ffreep,
+	 x86_tune_inter_unit_moves, x86_tune_inter_unit_conversions,
+	 x86_tune_use_bt, x86_tune_pad_returns, x86_tune_slow_imul_imm32_mem,
+	 x86_tune_slow_imul_imm8, x86_tune_fuse_cmp_and_branch): 
+	Enable/disable for bdver1.
+	(processor_target_table): Add bdver1_cost.
+	(cpu_names): Add bdver1.
+	(override_options): Set up PROCESSOR_BDVER1 for bdver1 entry in
+	 processor_alias_table.
+	(ix86_expand_vector_move_misalign): Change 
+	 TARGET_SSE_UNALIGNED_MOVE_OPTIMAL to TARGET_SSE_UNALIGNED_LOAD_OPTIMAL.
+	 Check for TARGET_SSE_UNALIGNED_STORE_OPTIMAL.
+	 Check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit movups instead
+	 of movupd/movdqu for SSE and AVX.
+	(ix86_tune_issue_rate): Add PROCESSOR_BDVER1.
+	(ix86_tune_adjust_cost): Add code for bdver1.
+	(standard_sse_constant_opcode): Add check for
+	TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit packed single xor instead
+	of packed double xor for SSE and AVX.
+
 2010-05-14  Pat Haugen  <pthaugen@us.ibm.com>
 
 	* tree-ssa-loop.prefetch.c (prune_ref_by_group_reuse): Cast abs()

gcc/config.gcc

@@ -1139,7 +1139,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i
 			need_64bit_hwint=yes
 			need_64bit_isa=yes
 			case X"${with_cpu}" in
-			Xgeneric|Xatom|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
+			Xgeneric|Xatom|Xcore2|Xnocona|Xx86-64|Xbdver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
 				;;
 			X)
 				if test x$with_cpu_64 = x; then
@@ -1148,7 +1148,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i
 				;;
 			*)
 				echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
-				echo "generic atom core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
+				echo "generic atom core2 nocona x86-64 bdver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
 				exit 1
 				;;
 			esac
@@ -1266,7 +1266,7 @@ i[34567]86-*-solaris2*)
 		need_64bit_isa=yes
 		use_gcc_stdint=wrap
 		case X"${with_cpu}" in
-		Xgeneric|Xatom|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
+		Xgeneric|Xatom|Xcore2|Xnocona|Xx86-64|Xbdver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
 			;;
 		X)
 			if test x$with_cpu_64 = x; then
@@ -1275,7 +1275,7 @@ i[34567]86-*-solaris2*)
 			;;
 		*)
 			echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
-			echo "generic atom core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
+			echo "generic atom core2 nocona x86-64 bdver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
 			exit 1
 			;;
 		esac
@@ -1346,7 +1346,7 @@ i[34567]86-*-mingw* | x86_64-*-mingw*)
 			if test x$enable_targets = xall; then
 				tm_defines="${tm_defines} TARGET_BI_ARCH=1"
 				case X"${with_cpu}" in
-				Xgeneric|Xatom|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
+				Xgeneric|Xatom|Xcore2|Xnocona|Xx86-64|Xbdver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
 					;;
 				X)
 					if test x$with_cpu_64 = x; then
@@ -1355,7 +1355,7 @@ i[34567]86-*-mingw* | x86_64-*-mingw*)
 					;;
 				*)
 					echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
-					echo "generic atom core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
+					echo "generic atom core2 nocona x86-64 bdver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
 					exit 1
 					;;
 				esac
@@ -2626,6 +2626,10 @@ case ${target} in
     ;;
   i686-*-* | i786-*-*)
     case ${target_noncanonical} in
+      bdver1-*)
+	arch=bdver1
+	cpu=bdver1
+	;;
       amdfam10-*|barcelona-*)
 	arch=amdfam10
 	cpu=amdfam10
@@ -2703,6 +2707,10 @@ case ${target} in
     ;;
   x86_64-*-*)
     case ${target_noncanonical} in
+      bdver1-*)
+	arch=bdver1
+	cpu=bdver1
+	;;
       amdfam10-*|barcelona-*)
 	arch=amdfam10
 	cpu=amdfam10
@@ -3109,8 +3117,8 @@ case "${target}" in
 				;;
 			"" | x86-64 | generic | native \
 			| k8 | k8-sse3 | athlon64 | athlon64-sse3 | opteron \
-			| opteron-sse3 | athlon-fx | amdfam10 | barcelona \
-			| nocona | core2 | atom)
+			| opteron-sse3 | athlon-fx | bdver1 | amdfam10 \
+			| barcelona | nocona | core2 | atom)
 				# OK
 				;;
 			*)

gcc/config/i386/driver-i386.c

@@ -396,6 +396,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
   unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
   unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0;
   unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
+  unsigned int has_fma4 = 0, has_xop = 0;
 
   bool arch;
 
@@ -460,6 +461,8 @@ const char *host_detect_local_cpu (int argc, const char **argv)
       has_sse4a = ecx & bit_SSE4a;
       has_abm = ecx & bit_ABM;
       has_lwp = ecx & bit_LWP;
+      has_fma4 = ecx & bit_FMA4;
+      has_xop = ecx & bit_XOP;
 
       has_longmode = edx & bit_LM;
       has_3dnowp = edx & bit_3DNOWP;
@@ -490,6 +493,8 @@ const char *host_detect_local_cpu (int argc, const char **argv)
 
       if (name == SIG_GEODE)
 	processor = PROCESSOR_GEODE;
+      else if (has_xop)
+	processor = PROCESSOR_BDVER1;
       else if (has_sse4a)
 	processor = PROCESSOR_AMDFAM10;
       else if (has_sse2 || has_longmode)
@@ -629,6 +634,9 @@ const char *host_detect_local_cpu (int argc, const char **argv)
     case PROCESSOR_AMDFAM10:
       cpu = "amdfam10";
       break;
+    case PROCESSOR_BDVER1:
+      cpu = "bdver1";
+      break;
 
     default:
       /* Use something reasonable.  */
@@ -674,6 +682,10 @@ const char *host_detect_local_cpu (int argc, const char **argv)
 	options = concat (options, " -mabm", NULL);
       if (has_lwp)
 	options = concat (options, " -mlwp", NULL);
+      if (has_fma4)
+	options = concat (options, " -mfma4", NULL);
+      if (has_xop)
+	options = concat (options, " -mxop", NULL);
 
       if (has_avx)
 	options = concat (options, " -mavx", NULL);

gcc/config/i386/i386-c.c

@@ -107,6 +107,10 @@ ix86_target_macros_internal (int isa_flag,
       def_or_undef (parse_in, "__amdfam10");
       def_or_undef (parse_in, "__amdfam10__");
       break;
+    case PROCESSOR_BDVER1:
+      def_or_undef (parse_in, "__bdver1");
+      def_or_undef (parse_in, "__bdver1__");
+      break;
     case PROCESSOR_PENTIUM4:
       def_or_undef (parse_in, "__pentium4");
       def_or_undef (parse_in, "__pentium4__");
@@ -182,6 +186,9 @@ ix86_target_macros_internal (int isa_flag,
     case PROCESSOR_AMDFAM10:
       def_or_undef (parse_in, "__tune_amdfam10__");
       break;
+    case PROCESSOR_BDVER1:
+      def_or_undef (parse_in, "__tune_bdver1__");
+      break;
     case PROCESSOR_PENTIUM4:
       def_or_undef (parse_in, "__tune_pentium4__");
       break;

gcc/config/i386/i386.h

@@ -240,6 +240,7 @@ extern const struct processor_costs ix86_size_cost;
 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
+#define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1)
 #define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)
 
 /* Feature tests against the various tunings.  */
@@ -277,7 +278,9 @@ enum ix86_tune_indices {
   X86_TUNE_INTEGER_DFMODE_MOVES,
   X86_TUNE_PARTIAL_REG_DEPENDENCY,
   X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY,
-  X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL,
+  X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL,
+  X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL,
+  X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL,
   X86_TUNE_SSE_SPLIT_REGS,
   X86_TUNE_SSE_TYPELESS_STORES,
   X86_TUNE_SSE_LOAD0_BY_PXOR,
@@ -352,8 +355,12 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST];
 	ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
 	ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
-#define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \
-	ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL]
+#define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
+	ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL]
+#define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \
+	ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL]
+#define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \
+	ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL]
 #define TARGET_SSE_SPLIT_REGS	ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
 #define TARGET_SSE_TYPELESS_STORES \
 	ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
@@ -591,6 +598,7 @@ enum target_cpu_default
   TARGET_CPU_DEFAULT_athlon_sse,
   TARGET_CPU_DEFAULT_k8,
   TARGET_CPU_DEFAULT_amdfam10,
+  TARGET_CPU_DEFAULT_bdver1,
 
   TARGET_CPU_DEFAULT_max
 };
@@ -2193,6 +2201,7 @@ enum processor_type
   PROCESSOR_GENERIC32,
   PROCESSOR_GENERIC64,
   PROCESSOR_AMDFAM10,
+  PROCESSOR_BDVER1,
   PROCESSOR_ATOM,
   PROCESSOR_max
 };

gcc/config/i386/i386.md

@@ -343,7 +343,7 @@
 
 ;; Processor type.
 (define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,atom,
-		    generic64,amdfam10"
+		    generic64,amdfam10,bdver1"
   (const (symbol_ref "ix86_schedule")))
 
 ;; A basic instruction type.  Refinements due to arguments to be
@@ -3113,9 +3113,15 @@
 	case MODE_V4SF:
 	  return "%vxorps\t%0, %d0";
 	case MODE_V2DF:
-	  return "%vxorpd\t%0, %d0";
+	  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+	    return "%vxorps\t%0, %d0";
+	  else
+	    return "%vxorpd\t%0, %d0";
 	case MODE_TI:
-	  return "%vpxor\t%0, %d0";
+	  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+	    return "%vxorps\t%0, %d0";
+	  else
+	    return "%vpxor\t%0, %d0";
 	default:
 	  gcc_unreachable ();
 	}
@@ -3127,9 +3133,15 @@
 	case MODE_V4SF:
 	  return "%vmovaps\t{%1, %0|%0, %1}";
 	case MODE_V2DF:
-	  return "%vmovapd\t{%1, %0|%0, %1}";
+	  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+	    return "%vmovaps\t{%1, %0|%0, %1}";
+	  else
+	    return "%vmovapd\t{%1, %0|%0, %1}";
 	case MODE_TI:
-	  return "%vmovdqa\t{%1, %0|%0, %1}";
+	  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+	    return "%vmovaps\t{%1, %0|%0, %1}";
+	  else
+	    return "%vmovdqa\t{%1, %0|%0, %1}";
 	case MODE_DI:
 	  return "%vmovq\t{%1, %0|%0, %1}";
 	case MODE_DF:
@@ -3263,9 +3275,15 @@
 	case MODE_V4SF:
 	  return "%vxorps\t%0, %d0";
 	case MODE_V2DF:
-	  return "%vxorpd\t%0, %d0";
+	  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+	    return "%vxorps\t%0, %d0";
+	  else
+	    return "%vxorpd\t%0, %d0";
 	case MODE_TI:
-	  return "%vpxor\t%0, %d0";
+	  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+	    return "%vxorps\t%0, %d0";
+	  else
+	    return "%vpxor\t%0, %d0";
 	default:
 	  gcc_unreachable ();
 	}
@@ -3277,9 +3295,15 @@
 	case MODE_V4SF:
 	  return "%vmovaps\t{%1, %0|%0, %1}";
 	case MODE_V2DF:
-	  return "%vmovapd\t{%1, %0|%0, %1}";
+	  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+	    return "%vmovaps\t{%1, %0|%0, %1}";
+	  else
+	    return "%vmovapd\t{%1, %0|%0, %1}";
 	case MODE_TI:
-	  return "%vmovdqa\t{%1, %0|%0, %1}";
+	  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+	    return "%vmovaps\t{%1, %0|%0, %1}";
+	  else
+	    return "%vmovdqa\t{%1, %0|%0, %1}";
 	case MODE_DI:
 	  return "%vmovq\t{%1, %0|%0, %1}";
 	case MODE_DF:
@@ -3403,9 +3427,15 @@
 	case MODE_V4SF:
 	  return "xorps\t%0, %0";
 	case MODE_V2DF:
-	  return "xorpd\t%0, %0";
+	  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+	    return "xorps\t%0, %0";
+	  else
+	    return "xorpd\t%0, %0";
 	case MODE_TI:
-	  return "pxor\t%0, %0";
+	  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+	    return "xorps\t%0, %0";
+	  else
+	    return "pxor\t%0, %0";
 	default:
 	  gcc_unreachable ();
 	}
@@ -3417,9 +3447,15 @@
 	case MODE_V4SF:
 	  return "movaps\t{%1, %0|%0, %1}";
 	case MODE_V2DF:
-	  return "movapd\t{%1, %0|%0, %1}";
+	  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+	    return "movaps\t{%1, %0|%0, %1}";
+	  else
+	    return "movapd\t{%1, %0|%0, %1}";
 	case MODE_TI:
-	  return "movdqa\t{%1, %0|%0, %1}";
+	  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+	    return "movaps\t{%1, %0|%0, %1}";
+	  else
+	    return "movdqa\t{%1, %0|%0, %1}";
 	case MODE_DI:
 	  return "movq\t{%1, %0|%0, %1}";
 	case MODE_DF:

gcc/config/i386/sse.md

@@ -194,9 +194,15 @@
 	  return "vmovaps\t{%1, %0|%0, %1}";
 	case MODE_V4DF:
 	case MODE_V2DF:
-	  return "vmovapd\t{%1, %0|%0, %1}";
+	  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+	    return "vmovaps\t{%1, %0|%0, %1}";
+	  else
+	    return "vmovapd\t{%1, %0|%0, %1}";
 	default:
-	  return "vmovdqa\t{%1, %0|%0, %1}";
+	  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+	    return "vmovaps\t{%1, %0|%0, %1}";
+	  else
+	    return "vmovdqa\t{%1, %0|%0, %1}";
 	}
     default:
       gcc_unreachable ();
@@ -236,9 +242,15 @@
 	case MODE_V4SF:
 	  return "movaps\t{%1, %0|%0, %1}";
 	case MODE_V2DF:
-	  return "movapd\t{%1, %0|%0, %1}";
+	  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+	    return "movaps\t{%1, %0|%0, %1}";
+	  else
+	    return "movapd\t{%1, %0|%0, %1}";
 	default:
-	  return "movdqa\t{%1, %0|%0, %1}";
+	  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+	    return "movaps\t{%1, %0|%0, %1}";
+	  else
+	    return "movdqa\t{%1, %0|%0, %1}";
 	}
     default:
       gcc_unreachable ();
@@ -1611,7 +1623,12 @@
 	  (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
   "AVX_VEC_FLOAT_MODE_P (<MODE>mode)
    && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
-  "v<logic>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
+{
+  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+    return "v<logic>ps\t{%2, %1, %0|%0, %1, %2}";
+  else
+    return "v<logic>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}";
+}
   [(set_attr "type" "sselog")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<avxvecmode>")])
@@ -1631,7 +1648,12 @@
 	  (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
   "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
    && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
-  "<logic>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
+{
+  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+    return "<logic>ps\t{%2, %0|%0, %2}";
+  else
+    return "<logic>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}";
+}
   [(set_attr "type" "sselog")
    (set_attr "mode" "<MODE>")])
 
@@ -1687,7 +1709,12 @@
 	  (match_operand:MODEF 1 "register_operand" "x")
 	  (match_operand:MODEF 2 "register_operand" "x")))]
   "AVX_FLOAT_MODE_P (<MODE>mode)"
-  "v<logic>p<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
+{
+  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+    return "v<logic>ps\t{%2, %1, %0|%0, %1, %2}";
+  else
+    return "v<logic>p<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}";
+}
   [(set_attr "type" "sselog")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<ssevecmode>")])
@@ -1698,7 +1725,12 @@
 	  (match_operand:MODEF 1 "register_operand" "0")
 	  (match_operand:MODEF 2 "register_operand" "x")))]
   "SSE_FLOAT_MODE_P (<MODE>mode)"
-  "<logic>p<ssemodefsuffix>\t{%2, %0|%0, %2}"
+{
+  if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
+    return "<logic>ps\t{%2, %0|%0, %2}";
+  else
+    return "<logic>p<ssemodefsuffix>\t{%2, %0|%0, %2}";
+}
   [(set_attr "type" "sselog")
    (set_attr "mode" "<ssevecmode>")])