Commit 10dc6e8c by Steve Ellcey Committed by Steve Ellcey

vect.md (vec_initv2si): Fix typo of V2SF to V2SI.

	* vect.md (vec_initv2si): Fix typo of V2SF to V2SI.
	Handle big endian vs. small endian.
	(vec_initv2sf): Handle big endian vs. small endian.
	(*vec_extractv2sf_1): Ditto.

From-SVN: r105008
parent 9f85ecfe
2005-10-05 Steve Ellcey <sje@cup.hp.com>
* vect.md (vec_initv2si): Fix typo of V2SF to V2SI.
Handle big endian vs. small endian.
(vec_initv2sf): Handle big endian vs. small endian.
(*vec_extractv2sf_1): Ditto.
2005-10-05 Dale Johannesen <dalej@apple.com> 2005-10-05 Dale Johannesen <dalej@apple.com>
* convert.c (convert_to_real): Don't convert * convert.c (convert_to_real): Don't convert
......
...@@ -791,7 +791,7 @@ ...@@ -791,7 +791,7 @@
[(set_attr "itanium_class" "mmshf")]) [(set_attr "itanium_class" "mmshf")])
(define_expand "vec_initv2si" (define_expand "vec_initv2si"
[(match_operand:V2SF 0 "gr_register_operand" "") [(match_operand:V2SI 0 "gr_register_operand" "")
(match_operand 1 "" "")] (match_operand 1 "" "")]
"" ""
{ {
...@@ -801,7 +801,10 @@ ...@@ -801,7 +801,10 @@
if (GET_CODE (op1) == CONST_INT && GET_CODE (op2) == CONST_INT) if (GET_CODE (op1) == CONST_INT && GET_CODE (op2) == CONST_INT)
{ {
x = gen_rtx_CONST_VECTOR (V2SImode, XVEC (operands[1], 0)); rtvec v = rtvec_alloc (2);
RTVEC_ELT (v, 0) = TARGET_BIG_ENDIAN ? op2 : op1;
RTVEC_ELT (v, 1) = TARGET_BIG_ENDIAN ? op1 : op2;;
x = gen_rtx_CONST_VECTOR (V2SImode, v);
emit_move_insn (operands[0], x); emit_move_insn (operands[0], x);
DONE; DONE;
} }
...@@ -811,7 +814,10 @@ ...@@ -811,7 +814,10 @@
if (!gr_reg_or_0_operand (op2, SImode)) if (!gr_reg_or_0_operand (op2, SImode))
op2 = force_reg (SImode, op2); op2 = force_reg (SImode, op2);
x = gen_rtx_VEC_CONCAT (V2SImode, op1, op2); if (TARGET_BIG_ENDIAN)
x = gen_rtx_VEC_CONCAT (V2SImode, op2, op1);
else
x = gen_rtx_VEC_CONCAT (V2SImode, op1, op2);
emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
DONE; DONE;
}) })
...@@ -1149,7 +1155,10 @@ ...@@ -1149,7 +1155,10 @@
if (!fr_reg_or_fp01_operand (op2, SFmode)) if (!fr_reg_or_fp01_operand (op2, SFmode))
op2 = force_reg (SFmode, op2); op2 = force_reg (SFmode, op2);
emit_insn (gen_fpack (operands[0], op1, op2)); if (TARGET_BIG_ENDIAN)
emit_insn (gen_fpack (operands[0], op2, op1));
else
emit_insn (gen_fpack (operands[0], op1, op2));
DONE; DONE;
}) })
...@@ -1275,7 +1284,10 @@ ...@@ -1275,7 +1284,10 @@
{ {
operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
operands[1] = gen_rtx_REG (DImode, REGNO (operands[1])); operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));
emit_insn (gen_lshrdi3 (operands[0], operands[1], GEN_INT (32))); if (TARGET_BIG_ENDIAN)
emit_move_insn (operands[0], operands[1]);
else
emit_insn (gen_lshrdi3 (operands[0], operands[1], GEN_INT (32)));
DONE; DONE;
}) })
......
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