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Commit 104ee20b by Alexandre Oliva Committed by Alexandre Oliva
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sh.h (GENERAL_REGISTER_P, [...]): New macros. 

* config/sh/sh.h (GENERAL_REGISTER_P,
GENERAL_OR_AP_REGISTER_P, FP_REGISTER_P, XD_REGISTER_P,
FP_OR_XD_REGISTER_P, FP_ANY_REGISTER_P): New macros.  Use them
all over.
(SPECIAL_REG): Renamed to SPECIAL_REGISTER_P.
* config/sh/sh.c: Use new macros.
* config/sh/sh.md: Likewise.

From-SVN: r37721
parent 5d00b10a
Showing with 65 additions and 41 deletions
gcc/ChangeLog
Fri Nov 24 19:54:36 2000 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (GENERAL_REGISTER_P,
GENERAL_OR_AP_REGISTER_P, FP_REGISTER_P, XD_REGISTER_P,
FP_OR_XD_REGISTER_P, FP_ANY_REGISTER_P): New macros. Use them
all over.
(SPECIAL_REG): Renamed to SPECIAL_REGISTER_P.
* config/sh/sh.c: Use new macros.
* config/sh/sh.md: Likewise.
Fri Nov 24 19:46:16 2000 Alexandre Oliva <aoliva@redhat.com> Fri Nov 24 19:46:16 2000 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md: Clobber MACH_REG and MACL_REG in SImode, * config/sh/sh.md: Clobber MACH_REG and MACL_REG in SImode,
......
gcc/config/sh/sh.c
...@@ -302,7 +302,7 @@ print_operand (stream, x, code) ...@@ -302,7 +302,7 @@ print_operand (stream, x, code)
switch (GET_CODE (x)) switch (GET_CODE (x))
{ {
case REG: case REG:
if (REGNO (x) >= FIRST_FP_REG && REGNO (x) <= LAST_FP_REG if (FP_REGISTER_P (REGNO (x))
&& GET_MODE_SIZE (GET_MODE (x)) > 4) && GET_MODE_SIZE (GET_MODE (x)) > 4)
fprintf ((stream), "d%s", reg_names[REGNO (x)]+1); fprintf ((stream), "d%s", reg_names[REGNO (x)]+1);
else else
...@@ -2084,8 +2084,7 @@ broken_move (insn) ...@@ -2084,8 +2084,7 @@ broken_move (insn)
know the current setting of fpscr, so disable fldi. */ know the current setting of fpscr, so disable fldi. */
&& (! TARGET_SH4 || TARGET_FMOVD) && (! TARGET_SH4 || TARGET_FMOVD)
&& GET_CODE (SET_DEST (pat)) == REG && GET_CODE (SET_DEST (pat)) == REG
&& REGNO (SET_DEST (pat)) >= FIRST_FP_REG && FP_REGISTER_P (REGNO (SET_DEST (pat))))
&& REGNO (SET_DEST (pat)) <= LAST_FP_REG)
&& (GET_CODE (SET_SRC (pat)) != CONST_INT && (GET_CODE (SET_SRC (pat)) != CONST_INT
|| ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat))))) || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat)))))
return 1; return 1;
...@@ -2211,10 +2210,7 @@ find_barrier (num_mova, mova, from) ...@@ -2211,10 +2210,7 @@ find_barrier (num_mova, mova, from)
/* See the code in machine_dependent_reorg, which has a similar if /* See the code in machine_dependent_reorg, which has a similar if
statement that generates a new mova insn in many cases. */ statement that generates a new mova insn in many cases. */
if (GET_CODE (dst) == REG if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
&& ((REGNO (dst) >= FIRST_FP_REG
&& REGNO (dst) <= LAST_XD_REG)
|| REGNO (dst) == FPUL_REG))
inc += 2; inc += 2;
} }
...@@ -3237,10 +3233,7 @@ machine_dependent_reorg (first) ...@@ -3237,10 +3233,7 @@ machine_dependent_reorg (first)
dst = gen_rtx_REG (HImode, REGNO (dst) + offset); dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
} }
if (GET_CODE (dst) == REG if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
&& ((REGNO (dst) >= FIRST_FP_REG
&& REGNO (dst) <= LAST_XD_REG)
|| REGNO (dst) == FPUL_REG))
{ {
/* This must be an insn that clobbers r0. */ /* This must be an insn that clobbers r0. */
rtx clobber = XVECEXP (PATTERN (scan), 0, rtx clobber = XVECEXP (PATTERN (scan), 0,
...@@ -3747,13 +3740,13 @@ push (rn) ...@@ -3747,13 +3740,13 @@ push (rn)
if (rn == FPUL_REG) if (rn == FPUL_REG)
x = gen_push_fpul (); x = gen_push_fpul ();
else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
&& rn >= FIRST_FP_REG && rn <= LAST_XD_REG) && FP_OR_XD_REGISTER_P (rn))
{ {
if ((rn - FIRST_FP_REG) & 1 && rn <= LAST_FP_REG) if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
return; return;
x = gen_push_4 (gen_rtx_REG (DFmode, rn)); x = gen_push_4 (gen_rtx_REG (DFmode, rn));
} }
else if (TARGET_SH3E && rn >= FIRST_FP_REG && rn <= LAST_FP_REG) else if (TARGET_SH3E && FP_REGISTER_P (rn))
x = gen_push_e (gen_rtx_REG (SFmode, rn)); x = gen_push_e (gen_rtx_REG (SFmode, rn));
else else
x = gen_push (gen_rtx_REG (SImode, rn)); x = gen_push (gen_rtx_REG (SImode, rn));
...@@ -3774,13 +3767,13 @@ pop (rn) ...@@ -3774,13 +3767,13 @@ pop (rn)
if (rn == FPUL_REG) if (rn == FPUL_REG)
x = gen_pop_fpul (); x = gen_pop_fpul ();
else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
&& rn >= FIRST_FP_REG && rn <= LAST_XD_REG) && FP_OR_XD_REGISTER_P (rn))
{ {
if ((rn - FIRST_FP_REG) & 1 && rn <= LAST_FP_REG) if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
return; return;
x = gen_pop_4 (gen_rtx_REG (DFmode, rn)); x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
} }
else if (TARGET_SH3E && rn >= FIRST_FP_REG && rn <= LAST_FP_REG) else if (TARGET_SH3E && FP_REGISTER_P (rn))
x = gen_pop_e (gen_rtx_REG (SFmode, rn)); x = gen_pop_e (gen_rtx_REG (SFmode, rn));
else else
x = gen_pop (gen_rtx_REG (SImode, rn)); x = gen_pop (gen_rtx_REG (SImode, rn));
...@@ -3867,9 +3860,9 @@ calc_live_regs (count_ptr, live_regs_mask2) ...@@ -3867,9 +3860,9 @@ calc_live_regs (count_ptr, live_regs_mask2)
else else
live_regs_mask |= 1 << reg; live_regs_mask |= 1 << reg;
count++; count++;
if (TARGET_SH4 && TARGET_FMOVD && reg >= FIRST_FP_REG) if (TARGET_SH4 && TARGET_FMOVD && FP_OR_XD_REGISTER_P (reg))
{ {
if (reg <= LAST_FP_REG) if (FP_REGISTER_P (reg))
{ {
if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1]) if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1])
{ {
...@@ -3880,7 +3873,7 @@ calc_live_regs (count_ptr, live_regs_mask2) ...@@ -3880,7 +3873,7 @@ calc_live_regs (count_ptr, live_regs_mask2)
count++; count++;
} }
} }
else if (reg <= LAST_XD_REG) else /* if (XD_REGISTER_P (reg)) */
{ {
/* Must switch to double mode to access these registers. */ /* Must switch to double mode to access these registers. */
target_flags &= ~FPU_SINGLE_BIT; target_flags &= ~FPU_SINGLE_BIT;
...@@ -4705,7 +4698,7 @@ fp_arith_reg_operand (op, mode) ...@@ -4705,7 +4698,7 @@ fp_arith_reg_operand (op, mode)
return 1; return 1;
return (regno >= FIRST_PSEUDO_REGISTER return (regno >= FIRST_PSEUDO_REGISTER
|| (regno >= FIRST_FP_REG && regno <= LAST_FP_REG)); || FP_REGISTER_P (regno));
} }
return 0; return 0;
} }
......
gcc/config/sh/sh.h
...@@ -441,7 +441,25 @@ do { \ ...@@ -441,7 +441,25 @@ do { \
#define FIRST_XD_REG XD0_REG #define FIRST_XD_REG XD0_REG
#define LAST_XD_REG (FIRST_XD_REG + 7) #define LAST_XD_REG (FIRST_XD_REG + 7)
#define SPECIAL_REG(REGNO) \ #define GENERAL_REGISTER_P(REGNO) \
((REGNO) >= FIRST_GENERAL_REG && (REGNO) <= LAST_GENERAL_REG)
#define GENERAL_OR_AP_REGISTER_P(REGNO) \
(GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
#define FP_REGISTER_P(REGNO) \
((REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG)
#define XD_REGISTER_P(REGNO) \
((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG)
#define FP_OR_XD_REGISTER_P(REGNO) \
(FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
#define FP_ANY_REGISTER_P(REGNO) \
(FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
#define SPECIAL_REGISTER_P(REGNO) \
((REGNO) == GBR_REG || (REGNO) == T_REG \ ((REGNO) == GBR_REG || (REGNO) == T_REG \
|| (REGNO) == MACH_REG || (REGNO) == MACL_REG) || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
...@@ -500,7 +518,7 @@ do { \ ...@@ -500,7 +518,7 @@ do { \
On the SH all but the XD regs are UNITS_PER_WORD bits wide. */ On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
#define HARD_REGNO_NREGS(REGNO, MODE) \ #define HARD_REGNO_NREGS(REGNO, MODE) \
((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG \ (XD_REGISTER_P (REGNO) \
? (GET_MODE_SIZE (MODE) / (2 * UNITS_PER_WORD)) \ ? (GET_MODE_SIZE (MODE) / (2 * UNITS_PER_WORD)) \
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
...@@ -517,16 +535,16 @@ do { \ ...@@ -517,16 +535,16 @@ do { \
and a secondary reload to reload from / to general regs; that and a secondary reload to reload from / to general regs; that
seems to be a loosing proposition. */ seems to be a loosing proposition. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \ #define HARD_REGNO_MODE_OK(REGNO, MODE) \
(SPECIAL_REG (REGNO) ? (MODE) == SImode \ (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
: (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \ : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
: (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG && (MODE) == SFmode \ : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
? 1 \ ? 1 \
: (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG \ : FP_REGISTER_P (REGNO) \
? ((MODE) == SFmode \ ? ((MODE) == SFmode \
|| (TARGET_SH3E && (MODE) == SCmode) \ || (TARGET_SH3E && (MODE) == SCmode) \
|| (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode) \ || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode) \
&& (((REGNO) - FIRST_FP_REG) & 1) == 0)) \ && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
: (REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG \ : XD_REGISTER_P (REGNO) \
? (MODE) == DFmode \ ? (MODE) == DFmode \
: (REGNO) == PR_REG ? 0 \ : (REGNO) == PR_REG ? 0 \
: (REGNO) == FPSCR_REG ? (MODE) == PSImode \ : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
...@@ -815,10 +833,10 @@ extern enum reg_class reg_class_from_letter[]; ...@@ -815,10 +833,10 @@ extern enum reg_class reg_class_from_letter[];
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \ #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS \ ((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS \
|| (CLASS) == DF_REGS) \ || (CLASS) == DF_REGS) \
&& (GET_CODE (X) == REG && REGNO (X) <= AP_REG)) \ && (GET_CODE (X) == REG && GENERAL_OR_AP_REGISTER_P (REGNO (X)))) \
|| (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS) \ || (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS) \
&& GET_CODE (X) == REG \ && GET_CODE (X) == REG \
&& REGNO (X) >= FIRST_FP_REG && REGNO (X) <= LAST_FP_REG)) \ && FP_REGISTER_P (REGNO (X)))) \
&& MODE == SFmode) \ && MODE == SFmode) \
? FPUL_REGS \ ? FPUL_REGS \
: ((CLASS) == FPUL_REGS \ : ((CLASS) == FPUL_REGS \
...@@ -829,7 +847,7 @@ extern enum reg_class reg_class_from_letter[]; ...@@ -829,7 +847,7 @@ extern enum reg_class reg_class_from_letter[];
|| system_reg_operand (X, VOIDmode))))) \ || system_reg_operand (X, VOIDmode))))) \
? GENERAL_REGS \ ? GENERAL_REGS \
: (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \ : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
&& GET_CODE (X) == REG && REGNO (X) > SP_REG \ && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
&& (CLASS) != REGNO_REG_CLASS (REGNO (X))) \ && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
? GENERAL_REGS : NO_REGS) ? GENERAL_REGS : NO_REGS)
...@@ -1265,7 +1283,8 @@ extern int current_function_anonymous_args; ...@@ -1265,7 +1283,8 @@ extern int current_function_anonymous_args;
has been allocated, which happens in local-alloc.c. */ has been allocated, which happens in local-alloc.c. */
#define REGNO_OK_FOR_BASE_P(REGNO) \ #define REGNO_OK_FOR_BASE_P(REGNO) \
((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG) (GENERAL_OR_AP_REGISTER_P (REGNO) \
|| GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
#define REGNO_OK_FOR_INDEX_P(REGNO) \ #define REGNO_OK_FOR_INDEX_P(REGNO) \
((REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG) ((REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
...@@ -1297,7 +1316,7 @@ extern int current_function_anonymous_args; ...@@ -1297,7 +1316,7 @@ extern int current_function_anonymous_args;
/* Nonzero if X is a hard reg that can be used as a base reg /* Nonzero if X is a hard reg that can be used as a base reg
or if it is a pseudo reg. */ or if it is a pseudo reg. */
#define REG_OK_FOR_BASE_P(X) \ #define REG_OK_FOR_BASE_P(X) \
(REGNO (X) <= AP_REG || REGNO (X) >= FIRST_PSEUDO_REGISTER) (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
/* Nonzero if X is a hard reg that can be used as an index /* Nonzero if X is a hard reg that can be used as an index
or if it is a pseudo reg. */ or if it is a pseudo reg. */
......
gcc/config/sh/sh.md
...@@ -2794,8 +2794,8 @@ ...@@ -2794,8 +2794,8 @@
(use (match_operand:PSI 2 "fpscr_operand" "c")) (use (match_operand:PSI 2 "fpscr_operand" "c"))
(clobber (match_scratch:SI 3 "X"))] (clobber (match_scratch:SI 3 "X"))]
"TARGET_SH4 && ! TARGET_FMOVD && reload_completed "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
&& true_regnum (operands[0]) >= FIRST_FP_REG && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
&& true_regnum (operands[1]) >= FIRST_FP_REG" && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
[(const_int 0)] [(const_int 0)]
" "
{ {
...@@ -2813,7 +2813,7 @@ ...@@ -2813,7 +2813,7 @@
(use (match_operand:PSI 2 "fpscr_operand" "c")) (use (match_operand:PSI 2 "fpscr_operand" "c"))
(clobber (match_scratch:SI 3 "X"))] (clobber (match_scratch:SI 3 "X"))]
"TARGET_SH4 && ! TARGET_FMOVD && reload_completed "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
&& true_regnum (operands[0]) >= FIRST_FP_REG && FP_OR_XD_REGISTER_P (operands[0])
&& find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))" && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
[(const_int 0)] [(const_int 0)]
" "
...@@ -2839,7 +2839,7 @@ ...@@ -2839,7 +2839,7 @@
(use (match_operand:PSI 2 "fpscr_operand" "c")) (use (match_operand:PSI 2 "fpscr_operand" "c"))
(clobber (match_scratch:SI 3 "X"))] (clobber (match_scratch:SI 3 "X"))]
"TARGET_SH4 && ! TARGET_FMOVD && reload_completed "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
&& true_regnum (operands[0]) >= FIRST_FP_REG" && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
[(const_int 0)] [(const_int 0)]
" "
{ {
...@@ -2880,7 +2880,7 @@ ...@@ -2880,7 +2880,7 @@
(use (match_operand:PSI 2 "fpscr_operand" "c")) (use (match_operand:PSI 2 "fpscr_operand" "c"))
(clobber (match_scratch:SI 3 "X"))] (clobber (match_scratch:SI 3 "X"))]
"TARGET_SH4 && ! TARGET_FMOVD && reload_completed "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
&& true_regnum (operands[1]) >= FIRST_FP_REG" && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
[(const_int 0)] [(const_int 0)]
" "
{ {
...@@ -4967,9 +4967,10 @@ ...@@ -4967,9 +4967,10 @@
(set (mem:SF (match_dup 0)) (set (mem:SF (match_dup 0))
(match_operand:SF 2 "general_movsrc_operand" ""))] (match_operand:SF 2 "general_movsrc_operand" ""))]
"REGNO (operands[0]) == 0 "REGNO (operands[0]) == 0
&& ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) >= FIRST_FP_REG) && ((GET_CODE (operands[2]) == REG
&& FP_OR_XD_REGISTER_P (REGNO (operands[2])))
|| (GET_CODE (operands[2]) == SUBREG || (GET_CODE (operands[2]) == SUBREG
&& REGNO (SUBREG_REG (operands[2])) >= FIRST_FP_REG)) && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
&& reg_unused_after (operands[0], insn)" && reg_unused_after (operands[0], insn)"
"fmov{.s|} %2,@(%0,%1)") "fmov{.s|} %2,@(%0,%1)")
...@@ -4980,9 +4981,10 @@ ...@@ -4980,9 +4981,10 @@
(mem:SF (match_dup 0)))] (mem:SF (match_dup 0)))]
"REGNO (operands[0]) == 0 "REGNO (operands[0]) == 0
&& ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) >= FIRST_FP_REG) && ((GET_CODE (operands[2]) == REG
&& FP_OR_XD_REGISTER_P (REGNO (operands[2])))
|| (GET_CODE (operands[2]) == SUBREG || (GET_CODE (operands[2]) == SUBREG
&& REGNO (SUBREG_REG (operands[2])) >= FIRST_FP_REG)) && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
&& reg_unused_after (operands[0], insn)" && reg_unused_after (operands[0], insn)"
"fmov{.s|} @(%0,%1),%2") "fmov{.s|} @(%0,%1),%2")
......
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