re PR target/81800 (On aarch64 ilp32 lrint should not be inlined as two instructions)

2017-10-26  Tamar Christina  <tamar.christina@arm.com>

	PR target/81800
	* config/aarch64/aarch64.md (lrint<GPF:mode><GPI:mode>2): Add flag_trapping_math
	and flag_fp_int_builtin_inexact.

gcc/testsuite/
2017-10-26  Tamar Christina  <tamar.christina@arm.com>

	* gcc.target/aarch64/inline-lrint_2.c (dg-options): Add -fno-trapping-math.

From-SVN: r254098

gcc/ChangeLog

+2017-10-26  Tamar Christina  <tamar.christina@arm.com>
+
+	PR target/81800
+	* config/aarch64/aarch64.md (lrint<GPF:mode><GPI:mode>2): Add flag_trapping_math
+	and flag_fp_int_builtin_inexact.
+
 2017-10-25  Palmer Dabbelt  <palmer@dabbelt.com>
 
 	* config/riscv/riscv.md (ZERO_EXTEND_LOAD): Define.

gcc/config/aarch64/aarch64.md

@@ -5155,7 +5155,9 @@
 (define_expand "lrint<GPF:mode><GPI:mode>2"
   [(match_operand:GPI 0 "register_operand")
    (match_operand:GPF 1 "register_operand")]
-  "TARGET_FLOAT"
+  "TARGET_FLOAT
+   && ((GET_MODE_SIZE (<GPF:MODE>mode) <= GET_MODE_SIZE (<GPI:MODE>mode))
+   || !flag_trapping_math || flag_fp_int_builtin_inexact)"
 {
   rtx cvt = gen_reg_rtx (<GPF:MODE>mode);
   emit_insn (gen_rint<GPF:mode>2 (cvt, operands[1]));

gcc/testsuite/ChangeLog

 2017-10-26  Tamar Christina  <tamar.christina@arm.com>
 
+	* gcc.target/aarch64/inline-lrint_2.c (dg-options): Add -fno-trapping-math.
+
+2017-10-26  Tamar Christina  <tamar.christina@arm.com>
+
 	* gcc.target/aarch64/advsimd-intrinsics/vect-dot-qi.h: New.
 	* gcc.target/aarch64/advsimd-intrinsics/vdot-compile.c: New.
 	* gcc.target/aarch64/advsimd-intrinsics/vect-dot-s8.c: New.

gcc/testsuite/gcc.target/aarch64/inline-lrint_2.c

 /* { dg-do compile } */
 /* { dg-require-effective-target ilp32 } */
-/* { dg-options "-O3 -fno-math-errno" } */
+/* { dg-options "-O3 -fno-math-errno -fno-trapping-math" } */
 
 #include "lrint-matherr.h"