Skip to content

R
riscv-gcc-1
Commit 0fcad513 by James Van Artsdalen
Options

(movsf,movdf): Use an input reload for MEM-MEM moves. 

(extendsfdf2): Don't allow GENERAL_REGS in any operand.
(truncdfsf2): Allocate a stack temp in expander.
Use that in the output function.
(fix_truncMN2,fixuns_truncMN2): Likewise.
Allocate scratch reg from Q_REGS.

From-SVN: r3830
parent 305f097e
Showing with 98 additions and 59 deletions
gcc/config/i386/i386.md
...@@ -858,8 +858,8 @@ ...@@ -858,8 +858,8 @@
;; GENERAL_REGS. For the purposes of regclass, prefer FLOAT_REGS. ;; GENERAL_REGS. For the purposes of regclass, prefer FLOAT_REGS.
(define_insn "movsf" (define_insn "movsf"
[(set (match_operand:SF 0 "general_operand" "=*rf,*rfm,f,!*rm") [(set (match_operand:SF 0 "general_operand" "=*rfm,*rf,f,!*rm")
(match_operand:SF 1 "general_operand" "*rfm,*rf,fG,fF"))] (match_operand:SF 1 "general_operand" "*rf,*rfm,fG,fF"))]
"" ""
"* "*
{ {
...@@ -959,8 +959,8 @@ ...@@ -959,8 +959,8 @@
;; GENERAL_REGS. For the purposes of regclass, prefer FLOAT_REGS. ;; GENERAL_REGS. For the purposes of regclass, prefer FLOAT_REGS.
(define_insn "movdf" (define_insn "movdf"
[(set (match_operand:DF 0 "general_operand" "=*rf,*rfm,f,!*rm") [(set (match_operand:DF 0 "general_operand" "=*rfm,*rf,f,!*rm")
(match_operand:DF 1 "general_operand" "*rfm,*rf,fG,fF"))] (match_operand:DF 1 "general_operand" "*rf,*rfm,fG,fF"))]
"" ""
"* "*
{ {
...@@ -1200,9 +1200,9 @@ ...@@ -1200,9 +1200,9 @@
;; Conversions between float and double. ;; Conversions between float and double.
(define_insn "extendsfdf2" (define_insn "extendsfdf2"
[(set (match_operand:DF 0 "general_operand" "=fm,f,f,!*r") [(set (match_operand:DF 0 "general_operand" "=fm,f")
(float_extend:DF (float_extend:DF
(match_operand:SF 1 "general_operand" "f,fm,!*r,f")))] (match_operand:SF 1 "general_operand" "f,fm")))]
"TARGET_80387" "TARGET_80387"
"* "*
{ {
...@@ -1234,14 +1234,27 @@ ...@@ -1234,14 +1234,27 @@
abort (); abort ();
}") }")
(define_expand "truncdfsf2"
[(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
(float_truncate:SF
(match_operand:DF 1 "register_operand" "")))
(clobber (match_dup 2))])]
"TARGET_80387"
"
{
operands[2] = (rtx) assign_386_stack_local (SFmode, 0);
}")
;; This cannot output into an f-reg because there is no way to be sure ;; This cannot output into an f-reg because there is no way to be sure
;; of truncating in that case. Otherwise this is just like a simple move ;; of truncating in that case. Otherwise this is just like a simple move
;; insn. ;; insn. So we pretend we can output to a reg in order to get better
;; register preferencing, but we really use a stack slot.
(define_insn "truncdfsf2" (define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,m") [(set (match_operand:SF 0 "nonimmediate_operand" "=f,m")
(float_truncate:SF (float_truncate:SF
(match_operand:DF 1 "register_operand" "0,f")))] (match_operand:DF 1 "register_operand" "0,f")))
(clobber (match_operand:SF 2 "memory_operand" "m,m"))]
"TARGET_80387" "TARGET_80387"
"* "*
{ {
...@@ -1256,18 +1269,8 @@ ...@@ -1256,18 +1269,8 @@
} }
else if (STACK_TOP_P (operands[0])) else if (STACK_TOP_P (operands[0]))
{ {
rtx xops[4]; output_asm_insn (AS1 (fstp%z2,%y2), operands);
return AS1 (fld%z2,%y2);
xops[0] = AT_SP (SFmode);
xops[1] = stack_pointer_rtx;
xops[2] = GEN_INT (GET_MODE_SIZE (SFmode));
xops[3] = operands[0];
output_asm_insn (AS2 (sub%L1,%2,%1), xops);
output_asm_insn (AS1 (fstp%z0,%y0), xops);
output_asm_insn (AS1 (fld%z0,%y0), xops);
output_asm_insn (AS2 (add%L1,%2,%1), xops);
RET;
} }
else else
abort (); abort ();
...@@ -1280,67 +1283,83 @@ ...@@ -1280,67 +1283,83 @@
;; part. ;; part.
(define_expand "fixuns_truncdfsi2" (define_expand "fixuns_truncdfsi2"
[(set (match_dup 5) [(set (match_dup 4)
(match_operand:DF 1 "register_operand" "")) (match_operand:DF 1 "register_operand" ""))
(parallel [(set (match_dup 3) (parallel [(set (match_dup 2)
(fix:DI (fix:DF (match_dup 5)))) (fix:DI (fix:DF (match_dup 4))))
(clobber (match_scratch:HI 2 "")) (clobber (match_dup 4))
(clobber (match_dup 5))]) (clobber (match_dup 5))
(clobber (match_dup 6))
(clobber (match_scratch:SI 7 ""))])
(set (match_operand:SI 0 "general_operand" "") (set (match_operand:SI 0 "general_operand" "")
(match_dup 4))] (match_dup 3))]
"TARGET_80387" "TARGET_80387"
" "
{ {
operands[3] = gen_reg_rtx (DImode); operands[2] = gen_reg_rtx (DImode);
operands[4] = gen_lowpart (SImode, operands[3]); operands[3] = gen_lowpart (SImode, operands[2]);
operands[5] = gen_reg_rtx (DFmode); operands[4] = gen_reg_rtx (DFmode);
operands[5] = (rtx) assign_386_stack_local (SImode, 0);
operands[6] = (rtx) assign_386_stack_local (SImode, 1);
}") }")
(define_expand "fixuns_truncsfsi2" (define_expand "fixuns_truncsfsi2"
[(set (match_dup 5) [(set (match_dup 4)
(match_operand:SF 1 "register_operand" "")) (match_operand:SF 1 "register_operand" ""))
(parallel [(set (match_dup 3) (parallel [(set (match_dup 2)
(fix:DI (fix:SF (match_dup 5)))) (fix:DI (fix:SF (match_dup 4))))
(clobber (match_scratch:HI 2 "")) (clobber (match_dup 4))
(clobber (match_dup 5))]) (clobber (match_dup 5))
(clobber (match_dup 6))
(clobber (match_scratch:SI 7 ""))])
(set (match_operand:SI 0 "general_operand" "") (set (match_operand:SI 0 "general_operand" "")
(match_dup 4))] (match_dup 3))]
"TARGET_80387" "TARGET_80387"
" "
{ {
operands[3] = gen_reg_rtx (DImode); operands[2] = gen_reg_rtx (DImode);
operands[4] = gen_lowpart (SImode, operands[3]); operands[3] = gen_lowpart (SImode, operands[2]);
operands[5] = gen_reg_rtx (SFmode); operands[4] = gen_reg_rtx (SFmode);
operands[5] = (rtx) assign_386_stack_local (SImode, 0);
operands[6] = (rtx) assign_386_stack_local (SImode, 1);
}") }")
;; Signed conversion to DImode. ;; Signed conversion to DImode.
(define_expand "fix_truncdfdi2" (define_expand "fix_truncdfdi2"
[(set (match_dup 3) [(set (match_dup 2)
(match_operand:DF 1 "register_operand" "")) (match_operand:DF 1 "register_operand" ""))
(parallel [(set (match_operand:DI 0 "general_operand" "") (parallel [(set (match_operand:DI 0 "general_operand" "")
(fix:DI (fix:DF (match_dup 3)))) (fix:DI (fix:DF (match_dup 2))))
(clobber (match_scratch:HI 2 "")) (clobber (match_dup 2))
(clobber (match_dup 3))])] (clobber (match_dup 3))
(clobber (match_dup 4))
(clobber (match_scratch:SI 5 ""))])]
"TARGET_80387" "TARGET_80387"
" "
{ {
operands[1] = copy_to_mode_reg (DFmode, operands[1]); operands[1] = copy_to_mode_reg (DFmode, operands[1]);
operands[3] = gen_reg_rtx (DFmode); operands[2] = gen_reg_rtx (DFmode);
operands[3] = (rtx) assign_386_stack_local (SImode, 0);
operands[4] = (rtx) assign_386_stack_local (SImode, 1);
}") }")
(define_expand "fix_truncsfdi2" (define_expand "fix_truncsfdi2"
[(set (match_dup 3) [(set (match_dup 2)
(match_operand:SF 1 "register_operand" "")) (match_operand:SF 1 "register_operand" ""))
(parallel [(set (match_operand:DI 0 "general_operand" "") (parallel [(set (match_operand:DI 0 "general_operand" "")
(fix:DI (fix:SF (match_dup 3)))) (fix:DI (fix:SF (match_dup 2))))
(clobber (match_scratch:HI 2 "")) (clobber (match_dup 2))
(clobber (match_dup 3))])] (clobber (match_dup 3))
(clobber (match_dup 4))
(clobber (match_scratch:SI 5 ""))])]
"TARGET_80387" "TARGET_80387"
" "
{ {
operands[1] = copy_to_mode_reg (SFmode, operands[1]); operands[1] = copy_to_mode_reg (SFmode, operands[1]);
operands[3] = gen_reg_rtx (SFmode); operands[2] = gen_reg_rtx (SFmode);
operands[3] = (rtx) assign_386_stack_local (SImode, 0);
operands[4] = (rtx) assign_386_stack_local (SImode, 1);
}") }")
;; These match a signed conversion of either DFmode or SFmode to DImode. ;; These match a signed conversion of either DFmode or SFmode to DImode.
...@@ -1348,16 +1367,20 @@ ...@@ -1348,16 +1367,20 @@
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "general_operand" "=rm") [(set (match_operand:DI 0 "general_operand" "=rm")
(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f")))) (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
(clobber (match_scratch:HI 2 "=&r")) (clobber (match_dup 1))
(clobber (match_dup 1))] (clobber (match_operand:SI 2 "memory_operand" "m"))
(clobber (match_operand:SI 3 "memory_operand" "m"))
(clobber (match_scratch:SI 4 "=&q"))]
"TARGET_80387" "TARGET_80387"
"* return (char *) output_fix_trunc (insn, operands);") "* return (char *) output_fix_trunc (insn, operands);")
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "general_operand" "=rm") [(set (match_operand:DI 0 "general_operand" "=rm")
(fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f")))) (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))
(clobber (match_scratch:HI 2 "=&r")) (clobber (match_dup 1))
(clobber (match_dup 1))] (clobber (match_operand:SI 2 "memory_operand" "m"))
(clobber (match_operand:SI 3 "memory_operand" "m"))
(clobber (match_scratch:SI 4 "=&q"))]
"TARGET_80387" "TARGET_80387"
"* return (char *) output_fix_trunc (insn, operands);") "* return (char *) output_fix_trunc (insn, operands);")
...@@ -1367,29 +1390,45 @@ ...@@ -1367,29 +1390,45 @@
[(parallel [(set (match_operand:SI 0 "general_operand" "") [(parallel [(set (match_operand:SI 0 "general_operand" "")
(fix:SI (fix:SI
(fix:DF (match_operand:DF 1 "register_operand" "")))) (fix:DF (match_operand:DF 1 "register_operand" ""))))
(clobber (match_scratch:HI 2 ""))])] (clobber (match_dup 2))
(clobber (match_dup 3))
(clobber (match_scratch:SI 4 ""))])]
"TARGET_80387" "TARGET_80387"
"") "
{
operands[2] = (rtx) assign_386_stack_local (SImode, 0);
operands[3] = (rtx) assign_386_stack_local (SImode, 1);
}")
(define_expand "fix_truncsfsi2" (define_expand "fix_truncsfsi2"
[(parallel [(set (match_operand:SI 0 "general_operand" "") [(parallel [(set (match_operand:SI 0 "general_operand" "")
(fix:SI (fix:SI
(fix:SF (match_operand:SF 1 "register_operand" "")))) (fix:SF (match_operand:SF 1 "register_operand" ""))))
(clobber (match_scratch:HI 2 ""))])] (clobber (match_dup 2))
(clobber (match_dup 3))
(clobber (match_scratch:SI 4 ""))])]
"TARGET_80387" "TARGET_80387"
"") "
{
operands[2] = (rtx) assign_386_stack_local (SImode, 0);
operands[3] = (rtx) assign_386_stack_local (SImode, 1);
}")
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "general_operand" "=rm") [(set (match_operand:SI 0 "general_operand" "=rm")
(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f")))) (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
(clobber (match_scratch:HI 2 "=&r"))] (clobber (match_operand:SI 2 "memory_operand" "m"))
(clobber (match_operand:SI 3 "memory_operand" "m"))
(clobber (match_scratch:SI 4 "=&q"))]
"TARGET_80387" "TARGET_80387"
"* return (char *) output_fix_trunc (insn, operands);") "* return (char *) output_fix_trunc (insn, operands);")
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "general_operand" "=rm") [(set (match_operand:SI 0 "general_operand" "=rm")
(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f")))) (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))
(clobber (match_scratch:HI 2 "=&r"))] (clobber (match_operand:SI 2 "memory_operand" "m"))
(clobber (match_operand:SI 3 "memory_operand" "m"))
(clobber (match_scratch:SI 4 "=&q"))]
"TARGET_80387" "TARGET_80387"
"* return (char *) output_fix_trunc (insn, operands);") "* return (char *) output_fix_trunc (insn, operands);")
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment